Lines Matching refs:tr1
3053 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
3055 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
3057 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]> {
3061 let OpKey = fp_mnemonic#!subst("VR", "FP", !cast<string>(tr1.op));
3087 TypedReg tr1, TypedReg tr2, bits<4> type> {
3089 def "" : InstVRRa<opcode, (outs tr1.op:$V1),
3092 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2))),
3095 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 0)>;
3097 def S : UnaryVRRa<mnemonic#"s", opcode, operator_cc, tr1, tr2,
3663 TypedReg tr1, TypedReg tr2, bits<4> type>
3664 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
3666 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3),
3677 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
3678 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
3680 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
3697 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0>
3698 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5),
3700 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
3712 TypedReg tr1, TypedReg tr2, bits<4> type = 0,
3714 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3716 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
3737 SDPatternOperator operator_cc, TypedReg tr1,
3739 def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
3742 def S : BinaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type,
3760 TypedReg tr1, TypedReg tr2, bits<4> type> {
3762 def "" : InstVRRb<opcode, (outs tr1.op:$V1),
3765 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))),
3768 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
3771 def S : BinaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type, 1>;
3785 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
3787 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3789 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
3794 let OpKey = fp_mnemonic#"MemFold"#!subst("VR", "FP", !cast<string>(tr1.op));
3818 SDPatternOperator operator_cc, TypedReg tr1,
3821 def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type,
3824 def S : BinaryVRRc<mnemonic#"s", opcode, operator_cc, tr1, tr2, type,
3851 TypedReg tr1, TypedReg tr2, bits<4> type>
3852 : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
3854 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3),
4409 TypedReg tr1, TypedReg tr2, ImmOpWithPattern imm, ImmOpWithPattern index>
4410 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
4412 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
4419 TypedReg tr1, TypedReg tr2, bits<4> type>
4420 : InstVRId<opcode, (outs tr1.op:$V1),
4423 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4435 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
4436 : InstVRRa<opcode, (outs tr1.op:$V1),
4439 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4452 TypedReg tr1, TypedReg tr2, bits<4> type,
4454 : InstVRRb<opcode, (outs tr1.op:$V1),
4457 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4470 TypedReg tr1, TypedReg tr2, bits<4> type,
4472 def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
4475 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
4478 def S : TernaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type,
4481 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
4496 TypedReg tr1, TypedReg tr2>
4497 : InstVRRc<opcode, (outs tr1.op:$V1),
4500 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4508 SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
4510 : InstVRRc<opcode, (outs tr1.op:$V1),
4513 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4527 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m6 = 0>
4528 : InstVRRd<opcode, (outs tr1.op:$V1),
4529 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
4531 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4533 (tr1.vt tr1.op:$V4)))]> {
4549 TypedReg tr1, TypedReg tr2, bits<4> type> {
4551 def "" : InstVRRd<opcode, (outs tr1.op:$V1),
4552 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, imm32zx4:$M6),
4555 (tr1.vt tr1.op:$V4)),
4556 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, 0)>;
4558 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
4559 tr2.op:$V3, tr1.op:$V4, 0)>;
4574 TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0,
4576 : InstVRRe<opcode, (outs tr1.op:$V1),
4577 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
4579 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4581 (tr1.vt tr1.op:$V4)))]> {
4584 let OpKey = fp_mnemonic#"MemFold"#!subst("VR", "FP", !cast<string>(tr1.op));
4594 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
4595 : InstVRSb<opcode, (outs tr1.op:$V1),
4598 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
4636 TypedReg tr1, TypedReg tr2, bits<5> bytes, ImmOpWithPattern index>
4637 : InstVRX<opcode, (outs tr1.op:$V1),
4640 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
4650 TypedReg tr1, TypedReg tr2, bits<4> type>
4651 : InstVRId<opcode, (outs tr1.op:$V1),
4654 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
4685 SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
4688 : InstVRRd<opcode, (outs tr1.op:$V1),
4691 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4710 TypedReg tr1, TypedReg tr2, bits<4> type,
4713 tr1, tr2, tr2, tr2, type,
4716 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
4720 tr1, tr2, tr2, tr2, type,
4723 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
5207 class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
5208 : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
5209 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]>;