Lines Matching refs:cls
2114 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2116 : InstRRE<opcode, (outs cls:$R1), (ins),
2118 [(set cls:$R1, (operator))]> {
2122 class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2123 : InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins),
2274 RegisterOperand cls, ImmOpWithPattern imm>
2275 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
2279 RegisterOperand cls, ImmOpWithPattern imm>
2280 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
2284 RegisterOperand cls, ImmOpWithPattern imm>
2285 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
2293 RegisterOperand cls, ImmOpWithPattern imm> {
2295 def "" : CmpBranchRIEa<mnemonic, opcode, cls, imm>;
2296 def Asm : AsmCmpBranchRIEa<mnemonic, opcode, cls, imm>;
2300 RegisterOperand cls>
2302 (ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4),
2306 RegisterOperand cls>
2308 (ins cls:$R1, cls:$R2, imm32zx4:$M3, brtarget16:$RI4),
2312 RegisterOperand cls>
2313 : InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4),
2321 RegisterOperand cls> {
2323 def "" : CmpBranchRIEb<mnemonic, opcode, cls>;
2324 def Asm : AsmCmpBranchRIEb<mnemonic, opcode, cls>;
2328 RegisterOperand cls, ImmOpWithPattern imm>
2330 (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4),
2334 RegisterOperand cls, ImmOpWithPattern imm>
2336 (ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4),
2340 RegisterOperand cls, ImmOpWithPattern imm>
2341 : InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4),
2349 RegisterOperand cls, ImmOpWithPattern imm> {
2351 def "" : CmpBranchRIEc<mnemonic, opcode, cls, imm>;
2352 def Asm : AsmCmpBranchRIEc<mnemonic, opcode, cls, imm>;
2356 RegisterOperand cls>
2357 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3),
2361 RegisterOperand cls>
2362 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3),
2366 RegisterOperand cls> {
2368 def "" : CmpBranchRRFc<mnemonic, opcode, cls>;
2369 def Asm : AsmCmpBranchRRFc<mnemonic, opcode, cls>;
2373 RegisterOperand cls>
2374 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2),
2382 RegisterOperand cls>
2384 (ins cls:$R1, cls:$R2, cond4:$M3, bdaddr12only:$BD4),
2388 RegisterOperand cls>
2390 (ins cls:$R1, cls:$R2, imm32zx4:$M3, bdaddr12only:$BD4),
2394 RegisterOperand cls>
2395 : InstRRS<opcode, (outs), (ins cls:$R1, cls:$R2, bdaddr12only:$BD4),
2403 RegisterOperand cls> {
2405 def "" : CmpBranchRRS<mnemonic, opcode, cls>;
2406 def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>;
2410 RegisterOperand cls, ImmOpWithPattern imm>
2412 (ins cls:$R1, imm:$I2, cond4:$M3, bdaddr12only:$BD4),
2416 RegisterOperand cls, ImmOpWithPattern imm>
2418 (ins cls:$R1, imm:$I2, imm32zx4:$M3, bdaddr12only:$BD4),
2422 RegisterOperand cls, ImmOpWithPattern imm>
2423 : InstRIS<opcode, (outs), (ins cls:$R1, imm:$I2, bdaddr12only:$BD4),
2431 RegisterOperand cls, ImmOpWithPattern imm> {
2433 def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>;
2434 def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>;
2438 RegisterOperand cls>
2439 : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, cond4:$M3),
2443 RegisterOperand cls>
2444 : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, imm32zx4:$M3),
2448 RegisterOperand cls> {
2450 def "" : CmpBranchRSYb<mnemonic, opcode, cls>;
2451 def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>;
2455 RegisterOperand cls>
2456 : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2),
2463 class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
2464 : InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2),
2470 class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls>
2471 : InstRILb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget32:$RI2),
2477 class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls>
2478 : InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2484 class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2485 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2491 class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
2492 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
2498 class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2499 : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr20only:$XBD2),
2505 class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
2506 : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2512 class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
2513 : InstRIEe<opcode, (outs cls:$R1),
2514 (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2520 class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
2521 : InstRSa<opcode, (outs cls:$R1),
2522 (ins cls:$R1src, cls:$R3, bdaddr12only:$BD2),
2528 class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2530 (outs cls:$R1), (ins cls:$R1src, cls:$R3, bdaddr20only:$BD2),
2536 class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2538 : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2543 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2545 : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2551 bits<16> rsyOpcode, RegisterOperand cls> {
2552 let DispKey = mnemonic # cls in {
2554 def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
2556 def Y : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
2560 class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls>
2561 : InstSSe<opcode, (outs cls:$R1, cls:$R3),
2580 RegisterOperand cls>
2581 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
2583 [(operator cls:$R1, pcrel32:$RI2)]> {
2592 RegisterOperand cls, bits<5> bytes,
2594 : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2596 [(operator cls:$R1, mode:$XBD2)]> {
2597 let OpKey = mnemonic#"r"#cls;
2604 RegisterOperand cls, bits<5> bytes,
2606 : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2608 [(operator cls:$R1, mode:$XBD2)]> {
2609 let OpKey = mnemonic#"r"#cls;
2616 SDPatternOperator operator, RegisterOperand cls,
2618 let DispKey = mnemonic # cls in {
2620 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
2622 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
2682 class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2684 : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
2689 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2691 : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
2697 bits<16> rsyOpcode, RegisterOperand cls> {
2698 let DispKey = mnemonic # cls in {
2700 def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
2702 def Y : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
2765 RegisterOperand cls, bits<5> bytes,
2767 : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$M3),
2777 RegisterOperand cls, bits<5> bytes,
2779 : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$M3),
2787 RegisterOperand cls, bits<5> bytes,
2789 : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2),
2799 RegisterOperand cls, bits<5> bytes,
2802 def "" : CondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2803 def Asm : AsmCondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2810 class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls>
2811 : InstRR<opcode, (outs), (ins cls:$R1),
2816 class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2818 : InstRRE<opcode, (outs), (ins cls:$R1),
2819 mnemonic#"\t$R1", [(operator cls:$R1)]> {
2894 class UnaryTiedRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2895 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src),
2912 RegisterOperand cls, ImmOpWithPattern imm>
2913 : InstRIa<opcode, (outs cls:$R1), (ins imm:$I2),
2915 [(set cls:$R1, (operator imm:$I2))]>;
2918 RegisterOperand cls, ImmOpWithPattern imm>
2919 : InstRILa<opcode, (outs cls:$R1), (ins imm:$I2),
2921 [(set cls:$R1, (operator imm:$I2))]>;
2924 RegisterOperand cls>
2925 : InstRILb<opcode, (outs cls:$R1), (ins pcrel32:$RI2),
2927 [(set cls:$R1, (operator pcrel32:$RI2))]> {
2936 SDPatternOperator operator, RegisterOperand cls,
2938 : InstRSYb<opcode, (outs cls:$R1),
2939 (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$M3),
2941 [(set cls:$R1,
2942 (z_select_ccmask (operator bdaddr20only:$BD2), cls:$R1src,
2949 let OpKey = mnemonic#"r"#cls;
2951 let MemKey = mnemonic#cls;
2958 RegisterOperand cls, bits<5> bytes,
2960 : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$M3),
2970 RegisterOperand cls, bits<5> bytes,
2972 : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
2985 RegisterOperand cls, bits<5> bytes,
2988 def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>;
2989 def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>;
2993 RegisterOperand cls, bits<5> bytes,
2995 : InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2),
2997 [(set cls:$R1, (operator mode:$XBD2))]> {
2998 let OpKey = mnemonic#"r"#cls;
3005 RegisterOperand cls, bits<5> bytes>
3006 : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
3008 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
3009 let OpKey = mnemonic#"r"#cls;
3017 RegisterOperand cls, bits<5> bytes,
3019 : InstRXYa<opcode, (outs cls:$R1), (ins mode:$XBD2),
3021 [(set cls:$R1, (operator mode:$XBD2))]> {
3022 let OpKey = mnemonic#"r"#cls;
3029 SDPatternOperator operator, RegisterOperand cls,
3031 let DispKey = mnemonic # cls in {
3033 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
3035 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
3139 RegisterOperand cls>
3140 : InstRXa<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
3144 RegisterOperand cls>
3145 : InstRXYa<opcode, (outs), (ins cls:$R1, bdxaddr20only:$XBD2),
3149 RegisterOperand cls>
3150 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
3269 let OpKey = mnemonic#cls;
3435 RegisterOperand cls, ImmOpWithPattern imm>
3436 : InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3438 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3444 RegisterOperand cls, ImmOpWithPattern imm>
3445 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
3447 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
3450 SDPatternOperator operator, RegisterOperand cls,
3454 def K : BinaryRIE<mnemonic#"k", opcode2, operator, cls, imm>,
3457 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
3461 class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3463 : InstRIEg<opcode, (outs cls:$R1),
3464 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
3466 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
3475 class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3477 : InstRIEg<opcode, (outs cls:$R1),
3478 (ins cls:$R1src, imm:$I2, imm32zx4:$M3),
3486 RegisterOperand cls, ImmOpWithPattern imm>
3487 : InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3497 RegisterOperand cls, ImmOpWithPattern imm> {
3499 def "" : CondBinaryRIE<mnemonic, opcode, cls, imm>;
3500 def Asm : AsmCondBinaryRIE<mnemonic, opcode, cls, imm>;
3504 RegisterOperand cls, ImmOpWithPattern imm>
3505 : InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3507 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3513 RegisterOperand cls>
3514 : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
3516 [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
3523 RegisterOperand cls>
3524 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
3526 [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
3529 SDPatternOperator operator, RegisterOperand cls> {
3532 def K : BinaryRSY<mnemonic#"k", opcode2, operator, cls>,
3535 def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
3539 class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
3540 : InstRSLb<opcode, (outs cls:$R1),
3547 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3549 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
3551 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
3552 let OpKey = mnemonic#"r"#cls;
3561 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
3562 : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
3564 [(set cls:$R1, (operator cls:$R1src,
3566 let OpKey = mnemonic#"r"#cls;
3581 let OpKey = mnemonic#"r"#cls;
3588 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3590 : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
3592 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
3593 let OpKey = mnemonic#"r"#cls;
3602 SDPatternOperator operator, RegisterOperand cls,
3604 let DispKey = mnemonic # cls in {
3606 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
3609 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
3635 let DispKey = mnemonic # cls in {
3643 class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
3644 : InstSSF<opcode, (outs cls:$R3), (ins bdaddr12pair:$BD1, bdaddr12pair:$BD2),
3840 class BinaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
3841 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3),
3906 class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
3908 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3914 class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
3916 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3923 bits<16> rsyOpcode, RegisterOperand cls,
3925 let DispKey = mnemonic # cls in {
3927 def "" : StoreBinaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
3929 def Y : StoreBinaryRSY<mnemonic#"y", rsyOpcode, cls, bytes,
3934 class StoreBinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
3936 (ins cls:$R1, bdladdr12onlylen8:$BDL2, imm32zx4:$M3),
3969 RegisterOperand cls>
3971 (ins bdraddr12only:$RBD1, bdaddr12only:$BD2, cls:$R3),
3995 RegisterOperand cls, ImmOpWithPattern imm>
3996 : InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2),
3998 [(set CC, (operator cls:$R1, imm:$I2))]> {
4003 RegisterOperand cls, ImmOpWithPattern imm>
4004 : InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2),
4006 [(set CC, (operator cls:$R1, imm:$I2))]> {
4011 RegisterOperand cls, SDPatternOperator load>
4012 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
4014 [(set CC, (operator cls:$R1, (load pcrel32:$RI2)))]> {
4024 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
4026 : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
4028 [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> {
4029 let OpKey = mnemonic#"r"#cls;
4037 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
4038 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
4040 [(set CC, (operator cls:$R1, (load bdxaddr12only:$XBD2)))]> {
4041 let OpKey = mnemonic#"r"#cls;
4050 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
4052 : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
4054 [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> {
4055 let OpKey = mnemonic#"r"#cls;
4063 SDPatternOperator operator, RegisterOperand cls,
4065 let DispKey = mnemonic # cls in {
4067 def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
4070 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
4075 class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4077 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
4083 class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4085 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
4092 RegisterOperand cls, bits<5> bytes> {
4093 let DispKey = mnemonic # cls in {
4095 def "" : CompareRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
4097 def Y : CompareRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
4192 RegisterOperand cls>
4193 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
4195 [(set CC, (operator cls:$R1, bdxaddr12only:$XBD2))]> {
4290 RegisterOperand cls>
4292 (ins bdaddr12only:$BD1, bdaddr12only:$BD2, cls:$R3),
4322 let OpKey = mnemonic#cls;
4328 class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4330 : InstRSb<opcode, (outs cls:$R1),
4331 (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
4340 class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4342 : InstRSYb<opcode, (outs cls:$R1),
4343 (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
4353 RegisterOperand cls, bits<5> bytes> {
4354 let DispKey = mnemonic # cls in {
4356 def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
4358 def Y : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
4400 let OpKey = mnemonic#"r"#cls;
4429 class TernaryVRIi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4431 (ins cls:$R2, imm32zx8:$I3, imm32zx4:$M4),
4594 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
4596 (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
4599 cls:$R3,
4606 class TernaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4607 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2,
4765 RegisterOperand cls>
4767 (ins cls:$R1, bdaddr12only:$BD2, cls:$R3, bdaddr12only:$BD4),
4771 RegisterOperand cls, AddressingMode mode = bdaddr20only>
4772 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
4774 [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
4790 RegisterOperand cls, AddressingMode mode = bdaddr12only>
4791 : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
4793 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
4801 RegisterOperand cls, AddressingMode mode = bdaddr20only>
4802 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
4804 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
4812 SDPatternOperator operator, RegisterOperand cls> {
4813 let DispKey = mnemonic # cls in {
4815 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
4817 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
4863 RegisterOperand cls> {
4864 def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
4866 def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
4886 class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
4888 : Pseudo<(outs cls:$R1), (ins imm:$I2),
4889 [(set cls:$R1, (operator imm:$I2))]>;
4893 RegisterOperand cls, bits<5> bytes,
4895 : Pseudo<(outs cls:$R1), (ins mode:$XBD2),
4896 [(set cls:$R1, (operator mode:$XBD2))]> {
4897 let OpKey = key#"r"#cls;
4915 class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
4917 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
4918 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
4923 class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
4925 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
4926 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
4930 RegisterOperand cls, ImmOpWithPattern imm> {
4933 def K : BinaryRIEPseudo<operator, cls, imm>,
4936 def "" : BinaryRIPseudo<operator, cls, imm>,
4945 class MemFoldPseudo<string mnemonic, RegisterOperand cls, bits<5> bytes,
4947 : Pseudo<(outs cls:$R1), (ins cls:$R2, mode:$XBD2), []> {
4950 mnemonic#"rk"#cls));
4952 let MemKey = mnemonic#cls;
4961 class MemFoldPseudo_FP<string mnemonic, RegisterOperand cls, bits<5> bytes,
4963 : MemFoldPseudo<mnemonic, cls, bytes, mode> {
4964 let OpKey = mnemonic#"r"#"MemFold"#cls;
4967 class MemFoldPseudo_FPTern<string mnemonic, RegisterOperand cls, bits<5> bytes,
4969 : Pseudo<(outs cls:$R1), (ins cls:$R2, cls:$R3, mode:$XBD2), []> {
4970 let OpKey = mnemonic#"r"#"MemFold"#cls;
4972 let MemKey = mnemonic#cls;
4981 class MemFoldPseudo_CondMove<string mnemonic, RegisterOperand cls, bits<5> bytes,
4983 : Pseudo<(outs cls:$R1),
4984 (ins cls:$R2, mode:$XBD2, cond4:$valid, cond4:$M3), []> {
4985 let OpKey = !subst("loc", "sel", mnemonic)#"r"#cls;
4987 let MemKey = mnemonic#cls;
4995 class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
4997 : Pseudo<(outs), (ins cls:$R1, imm:$I2),
4998 [(set CC, (operator cls:$R1, imm:$I2))]> {
5003 class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
5006 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
5007 [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> {
5053 class CondBinaryRIEPseudo<RegisterOperand cls, ImmOpWithPattern imm>
5054 : Pseudo<(outs cls:$R1),
5055 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
5056 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
5066 RegisterOperand cls, bits<5> bytes,
5068 : Pseudo<(outs cls:$R1),
5069 (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
5070 [(set cls:$R1,
5071 (z_select_ccmask (operator mode:$BD2), cls:$R1src,
5078 let OpKey = mnemonic#"r"#cls;
5080 let MemKey = mnemonic#cls;
5086 class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes,
5088 : Pseudo<(outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3), []> {
5095 class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
5097 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
5098 [(operator cls:$R1, mode:$XBD2)]> {
5118 class SelectWrapper<ValueType vt, RegisterOperand cls>
5119 : Pseudo<(outs cls:$dst),
5120 (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc),
5121 [(set (vt cls:$dst), (z_select_ccmask cls:$src1, cls:$src2,
5129 multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
5134 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
5135 [(store (z_select_ccmask cls:$new, (load mode:$addr),
5139 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
5140 [(store (z_select_ccmask (load mode:$addr), cls:$new,
5148 class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
5150 : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
5151 [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
5224 class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls,
5226 : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
5227 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
5232 class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls,
5234 : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
5235 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
5240 class BinaryAliasVRRf<RegisterOperand cls>
5241 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;
5244 class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls,
5246 : Alias<4, (outs), (ins cls:$R1, imm:$I2),
5247 [(set CC, (operator cls:$R1, imm:$I2))]> {
5274 SDPatternOperator operator, RegisterOperand cls,
5277 def "" : BinaryRXY<mnemonic, opcode, operator, cls, load, bytes, mode> {
5278 let MemKey = mnemonic#cls;
5282 def _MemFoldPseudo : MemFoldPseudo<mnemonic, cls, bytes, mode>;
5287 RegisterOperand cls,
5289 let DispKey = mnemonic # cls in {
5290 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
5293 let MemKey = mnemonic#cls;
5297 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load,
5300 def _MemFoldPseudo : MemFoldPseudo<mnemonic, cls, bytes, bdxaddr12pair>;
5304 SDPatternOperator operator, RegisterOperand cls,
5306 def "" : BinaryRXE<mnemonic, opcode, operator, cls, load, bytes> {
5307 let MemKey = mnemonic#cls;
5310 def _MemFoldPseudo : MemFoldPseudo_FP<mnemonic, cls, bytes, bdxaddr12pair>;
5326 RegisterOperand cls, bits<5> bytes,
5328 defm "" : CondUnaryRSYPair<mnemonic, opcode, operator, cls, bytes, mode>;
5329 def _MemFoldPseudo : MemFoldPseudo_CondMove<mnemonic, cls, bytes, mode>;
5334 RegisterOperand cls, bits<5> bytes,
5336 def "" : CondUnaryRSYPseudo<mnemonic, operator, cls, bytes, mode>;
5337 def _MemFoldPseudo : MemFoldPseudo_CondMove<mnemonic, cls, bytes, mode>;