Lines Matching refs:VR128
2127 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
2569 def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2573 def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2638 : InstVRX<opcode, (outs), (ins VR128:$V1, bdxaddr12only:$XBD2, imm32zx4:$M3),
2646 (ins VR128:$V1, bdxaddr12only:$XBD2, imm32zx4:$M3),
2649 def "" : InstVRX<opcode, (outs), (ins VR128:$V1, bdxaddr12only:$XBD2),
2656 : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
2658 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2666 : InstVRSd<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
2668 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2675 : InstVSI<opcode, (outs), (ins VR128:$V1, bdaddr12only:$BD2, imm32zx8:$I3),
2677 [(operator VR128:$V1, imm32zx8:$I3, bdaddr12only:$BD2)]> {
2708 def Align : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
2712 def "" : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
3049 : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
3067 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
3074 : InstVRRa<opcode, (outs VR128:$V1),
3075 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4),
3103 def "" : InstVRRa<opcode, (outs VR128:$V1),
3104 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5),
3107 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2,
3122 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
3129 def Align : InstVRX<opcode, (outs VR128:$V1),
3133 def "" : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2),
3658 : InstVRIb<opcode, (outs VR128:$V1),
3672 : InstVRIc<opcode, (outs VR128:$V1),
3673 (ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4),
3687 : InstVRIe<opcode, (outs VR128:$V1),
3688 (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
3692 : InstVRIh<opcode, (outs VR128:$V1),
3707 : InstVRRa<opcode, (outs VR128:$V1),
3708 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
3723 : InstVRRb<opcode, (outs VR128:$V1), (ins VR128:$V2, VR128:$V3, imm32zx4:$M5),
3729 : InstVRRb<opcode, (outs VR128:$V1),
3730 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3747 : InstVRRb<opcode, (outs VR128:$V1),
3748 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3776 def "" : InstVRRb<opcode, (outs VR128:$V1),
3777 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3780 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
3800 : InstVRRc<opcode, (outs VR128:$V1),
3801 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4),
3808 : InstVRRc<opcode, (outs VR128:$V1),
3809 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3829 : InstVRRc<opcode, (outs VR128:$V1),
3830 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
3841 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3),
3847 : InstVRRk<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
3860 : InstVRSa<opcode, (outs VR128:$V1),
3861 (ins VR128:$V3, shift12only:$BD2, imm32zx4:$M4),
3866 : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
3868 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
3884 (ins VR128:$V3, shift12only:$BD2, imm32zx4: $M4),
3889 : InstVRSd<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
3891 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
3898 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
3943 : InstVSI<opcode, (outs VR128:$V1), (ins bdaddr12only:$BD2, imm32zx8:$I3),
3945 [(set VR128:$V1, (operator imm32zx8:$I3, bdaddr12only:$BD2))]> {
3952 : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
4164 : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4180 : InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4212 : InstVRRg<opcode, (outs), (ins VR128:$V1),
4430 : InstVRIi<opcode, (outs VR128:$V1),
4447 : InstVRRa<opcode, (outs VR128:$V1),
4448 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
4487 def "" : InstVRRb<opcode, (outs VR128:$V1),
4488 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
4491 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4521 : InstVRRc<opcode, (outs VR128:$V1),
4522 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
4539 : InstVRRd<opcode, (outs VR128:$V1),
4540 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5),
4564 def "" : InstVRRd<opcode, (outs VR128:$V1),
4565 (ins VR128:$V2, VR128:$V3, VR128:$V4,
4569 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4570 VR128:$V4, imm32zx4:$M5, 0)>;
4589 : InstVRRe<opcode, (outs VR128:$V1),
4590 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4607 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2,
4612 : InstVRRj<opcode, (outs VR128:$V1), (ins VR128:$V2,
4613 VR128:$V3, imm32zx4:$M4),
4617 : InstVRSb<opcode, (outs VR128:$V1),
4618 (ins VR128:$V1src, GR64:$R3, shift12only:$BD2, imm32zx4:$M4),
4626 : InstVRV<opcode, (outs VR128:$V1),
4627 (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3),
4664 : InstVRId<opcode, (outs VR128:$V1),
4665 (ins VR128:$V1src, VR128:$V2, VR128:$V3,
4673 : InstVRIf<opcode, (outs VR128:$V1),
4674 (ins VR128:$V2, VR128:$V3,
4679 : InstVRIg<opcode, (outs VR128:$V1),
4680 (ins VR128:$V2, imm32zx8:$I3,
4700 : InstVRRd<opcode, (outs VR128:$V1),
4701 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4731 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4732 VR128:$V4, imm32zx4_timm:$M5, 0)>;
5241 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;