Lines Matching refs:BitShift
4212 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr, in lowerATOMIC_LOAD_OP() local
4214 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift); in lowerATOMIC_LOAD_OP()
4219 DAG.getConstant(0, DL, WideVT), BitShift); in lowerATOMIC_LOAD_OP()
4236 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, in lowerATOMIC_LOAD_OP()
4243 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift, in lowerATOMIC_LOAD_OP()
4328 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr, in lowerATOMIC_CMP_SWAP() local
4330 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift); in lowerATOMIC_CMP_SWAP()
4335 DAG.getConstant(0, DL, WideVT), BitShift); in lowerATOMIC_CMP_SWAP()
4339 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift, in lowerATOMIC_CMP_SWAP()
7791 Register BitShift = IsSubWord ? MI.getOperand(4).getReg() : Register(); in emitAtomicLoadBinary() local
7844 .addReg(OldVal).addReg(BitShift).addImm(0); in emitAtomicLoadBinary()
7908 Register BitShift = (IsSubWord ? MI.getOperand(4).getReg() : Register()); in emitAtomicLoadMinMax() local
7960 .addReg(OldVal).addReg(BitShift).addImm(0); in emitAtomicLoadMinMax()
8021 Register BitShift = MI.getOperand(5).getReg(); in emitAtomicCmpSwapW() local
8081 .addReg(OldVal).addReg(BitShift).addImm(BitSize); in emitAtomicCmpSwapW()