100 static unsigned log2LdstWidth(unsigned Opcode) {  in log2LdstWidth()  argument
101   switch (Opcode) {  in log2LdstWidth()
119 static uint8_t compressedLDSTOffsetMask(unsigned Opcode) {  in compressedLDSTOffsetMask()  argument
120   return 0x1f << log2LdstWidth(Opcode);  in compressedLDSTOffsetMask()
125 static bool compressibleSPOffset(int64_t Offset, unsigned Opcode) {  in compressibleSPOffset()  argument
126   return log2LdstWidth(Opcode) == 2 ? isShiftedUInt<6, 2>(Offset)  in compressibleSPOffset()
133 static int64_t getBaseAdjustForCompression(int64_t Offset, unsigned Opcode) {  in getBaseAdjustForCompression()  argument
135   return Offset & ~compressedLDSTOffsetMask(Opcode);  in getBaseAdjustForCompression()
148   const unsigned Opcode = MI.getOpcode();  in isCompressibleLoad()  local
150   return Opcode == RISCV::LW || (!STI.is64Bit() && Opcode == RISCV::FLW) ||  in isCompressibleLoad()
151          Opcode == RISCV::LD || Opcode == RISCV::FLD;  in isCompressibleLoad()
157   const unsigned Opcode = MI.getOpcode();  in isCompressibleStore()  local
159   return Opcode == RISCV::SW || (!STI.is64Bit() && Opcode == RISCV::FSW) ||  in isCompressibleStore()
160          Opcode == RISCV::SD || Opcode == RISCV::FSD;  in isCompressibleStore()
176   const unsigned Opcode = MI.getOpcode();  in getRegImmPairPreventingCompression()  local
184     int64_t NewBaseAdjust = getBaseAdjustForCompression(Offset, Opcode);  in getRegImmPairPreventingCompression()
190       if (!compressibleSPOffset(Offset, Opcode) && NewBaseAdjust)  in getRegImmPairPreventingCompression()
289   unsigned Opcode = MI.getOpcode();  in updateOperands()  local
322   int64_t NewOffset = MOImm.getImm() & compressedLDSTOffsetMask(Opcode);  in updateOperands()
367         unsigned Opcode = RISCV::FPR32RegClass.contains(RegImm.Reg)  in runOnMachineFunction()  local
370         BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(Opcode), NewReg)  in runOnMachineFunction()