Lines Matching refs:SDValue
366 bool isZExtFree(SDValue Val, EVT VT2) const override;
371 bool hasAndNotCompare(SDValue Y) const override;
372 bool hasBitTest(SDValue X, SDValue Y) const override;
374 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
379 bool shouldScalarizeBinop(SDValue VecOp) const override;
407 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
408 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
411 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
413 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
417 void computeKnownBitsForTargetNode(const SDValue Op,
422 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
440 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
441 std::vector<SDValue> &Ops,
507 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
511 SmallVectorImpl<SDValue> &InVals) const override;
516 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
518 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
520 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
521 SmallVectorImpl<SDValue> &InVals) const override;
529 SDValue C) const override;
531 bool isMulAddWithConstProfitable(SDValue AddNode,
532 SDValue ConstNode) const override;
556 SDValue Val, SDValue *Parts,
560 SDValue
562 const SDValue *Parts, unsigned NumParts,
591 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
624 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
625 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
627 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
629 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
630 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
631 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
632 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
633 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
634 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
635 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
636 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
637 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
638 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
639 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
640 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
641 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
642 SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
643 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
645 SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
646 SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
647 SDValue lowerVectorFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
648 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
649 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
650 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
651 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
652 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
653 SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
654 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
655 SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,
657 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
658 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
659 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
660 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
661 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
662 SDValue lowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
663 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
664 SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const;
665 SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const;
666 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
668 SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const;
669 SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const;
670 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
671 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
672 SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
673 SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG,
676 SDValue lowerFixedLengthVectorShiftToRVV(SDValue Op, SelectionDAG &DAG) const;
677 SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
679 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
681 SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc) const;
682 SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG, unsigned MaskOpc,
684 SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
685 SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const;
686 SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG,
688 SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
690 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
691 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
693 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
695 SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
696 SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
705 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,