Lines Matching refs:RISCVAsmBackend

30 Optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {  in getFixupKind()
48 RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {  in getFixupKindInfo()
116 bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,  in shouldForceRelocation()
140 bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup,  in fixupNeedsRelaxationAdvanced()
168 void RISCVAsmBackend::relaxInstruction(MCInst &Inst,  in relaxInstruction()
205 bool RISCVAsmBackend::relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF,  in relaxDwarfLineAddr()
275 bool RISCVAsmBackend::relaxDwarfCFA(MCDwarfCallFrameFragment &DF,  in relaxDwarfCFA()
336 unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {  in getRelaxedOpcode()
350 bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,  in mayNeedRelaxation()
355 bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,  in writeNopData()
488 bool RISCVAsmBackend::evaluateTargetFixup(  in evaluateTargetFixup()
549 void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,  in applyFixup()
583 bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(  in shouldInsertExtraNopBytesForCodeAlign()
606 bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,  in shouldInsertFixupForCodeAlign()
636 RISCVAsmBackend::createObjectTargetWriter() const {  in createObjectTargetWriter()
646   return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);  in createRISCVAsmBackend()