Lines Matching refs:XT

24 //             * FRT/RT/VT/XT/BT - target register
48 //          The operand is an 8-bit immediate (IMM), the destination (XT)
283   bits<6> XT;
297   let Inst{37} = XT{5};
298   let Inst{38-42} = XT{4-0};
307   bits<6> XT;
312   let Inst{6-10} = XT{4-0};
316   let Inst{31} = XT{5};
323     bits<6> XT;
340     let Inst{38-42} = XT{4-0};
348     let Inst{63} = XT{5};
441   bits<6> XT;
454   let Inst{38-42} = XT{4-0};
456   let Inst{47} = XT{5};
466   bits<6> XT;
480   let Inst{38-42} = XT{4-0};
483   let Inst{47} = XT{5};
490   bits<6> XT;
504   let Inst{38-42} = XT{4-0};
512   let Inst{63} = XT{5};
519   bits<6> XT;
535   let Inst{38-42} = XT{4-0};
543   let Inst{63} = XT{5};
634       8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XT), (ins memri34:$D_RA),
636                                      "plxv $XT, $D_RA", IIC_LdStLFD>;
838   bits<6> XT;
843   let Inst{6-10} = XT{4-0};
847   let Inst{31} = XT{5};
1276     8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1278                             "xxpermx $XT, $XA, $XB, $XC, $UIM",
1281     8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1282                        vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC",
1285     8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1286                        vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC",
1289     8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1290                        vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC",
1293     8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1294                        vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC",
1301   def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
1303                                      "xxspltiw $XT, $IMM32", IIC_VecGeneral,
1305   def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT),
1307                                       "xxspltidp $XT, $IMM32", IIC_VecGeneral,
1308                                       [(set v2f64:$XT,
1311       8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT),
1313                              "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral,
1314                              [(set v2i64:$XT,
1317                              RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
1631      8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
1633                             "xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral,
1634                             [(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA,
1653      XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
1654                         "xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
1656      XForm_XT6_IMM5_VB5<60, 917, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
1657                         "xxgenpcvhm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
1659      XForm_XT6_IMM5_VB5<60, 948, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
1660                         "xxgenpcvwm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
1662      XForm_XT6_IMM5_VB5<60, 949, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM),
1663                         "xxgenpcvdm $XT, $VRB, $IMM", IIC_VecGeneral, []>;
1818   def LXVKQ : XForm_XT6_IMM5<60, 31, 360, (outs vsrc:$XT), (ins u5imm:$UIM),
1819                              "lxvkq $XT, $UIM", IIC_VecGeneral, []>;
1974   def : Pat <(v2i64 (PPCxxsplti32dx v2i64:$XT, i32:$XI, i32:$IMM32)),
1975              (v2i64 (XXSPLTI32DX v2i64:$XT, i32:$XI, i32:$IMM32))>;