Lines Matching refs:PPC
91 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP, in PPCInstrInfo()
93 STI.isPPC64() ? PPC::BLR8 : PPC::BLR), in PPCInstrInfo()
103 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || in CreateTargetHazardRecognizer()
104 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { in CreateTargetHazardRecognizer()
122 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) in CreateTargetPostRAHazardRecognizer()
126 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && in CreateTargetPostRAHazardRecognizer()
127 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { in CreateTargetPostRAHazardRecognizer()
183 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
184 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
186 IsRegCR = PPC::CRRCRegClass.contains(Reg) || in getOperandLatency()
187 PPC::CRBITRCRegClass.contains(Reg); in getOperandLatency()
199 case PPC::DIR_7400: in getOperandLatency()
200 case PPC::DIR_750: in getOperandLatency()
201 case PPC::DIR_970: in getOperandLatency()
202 case PPC::DIR_E5500: in getOperandLatency()
203 case PPC::DIR_PWR4: in getOperandLatency()
204 case PPC::DIR_PWR5: in getOperandLatency()
205 case PPC::DIR_PWR5X: in getOperandLatency()
206 case PPC::DIR_PWR6: in getOperandLatency()
207 case PPC::DIR_PWR6X: in getOperandLatency()
208 case PPC::DIR_PWR7: in getOperandLatency()
209 case PPC::DIR_PWR8: in getOperandLatency()
256 case PPC::FADD: in isAssociativeAndCommutative()
257 case PPC::FADDS: in isAssociativeAndCommutative()
259 case PPC::FMUL: in isAssociativeAndCommutative()
260 case PPC::FMULS: in isAssociativeAndCommutative()
262 case PPC::VADDFP: in isAssociativeAndCommutative()
264 case PPC::XSADDDP: in isAssociativeAndCommutative()
265 case PPC::XVADDDP: in isAssociativeAndCommutative()
266 case PPC::XVADDSP: in isAssociativeAndCommutative()
267 case PPC::XSADDSP: in isAssociativeAndCommutative()
269 case PPC::XSMULDP: in isAssociativeAndCommutative()
270 case PPC::XVMULDP: in isAssociativeAndCommutative()
271 case PPC::XVMULSP: in isAssociativeAndCommutative()
272 case PPC::XSMULSP: in isAssociativeAndCommutative()
277 case PPC::MULHD: in isAssociativeAndCommutative()
278 case PPC::MULLD: in isAssociativeAndCommutative()
279 case PPC::MULHW: in isAssociativeAndCommutative()
280 case PPC::MULLW: in isAssociativeAndCommutative()
303 {PPC::XSMADDADP, PPC::XSADDDP, PPC::XSMULDP, 1, 2, PPC::XSSUBDP},
304 {PPC::XSMADDASP, PPC::XSADDSP, PPC::XSMULSP, 1, 2, PPC::XSSUBSP},
305 {PPC::XVMADDADP, PPC::XVADDDP, PPC::XVMULDP, 1, 2, PPC::XVSUBDP},
306 {PPC::XVMADDASP, PPC::XVADDSP, PPC::XVMULSP, 1, 2, PPC::XVSUBSP},
307 {PPC::FMADD, PPC::FADD, PPC::FMUL, 3, 1, PPC::FSUB},
308 {PPC::FMADDS, PPC::FADDS, PPC::FMULS, 3, 1, PPC::FSUBS}};
451 if (Opcode != PPC::XSMADDASP && Opcode != PPC::XSMADDADP) in getFMAPatterns()
595 if (Operand.getReg() == PPC::ZERO8) { in finalizeInsInstrs()
668 *MBB->getParent(), PPC::RegisterPressureSets::VSSRC); in shouldReduceRegisterPressure()
671 return GetMBBPressure(MBB)[PPC::RegisterPressureSets::VSSRC] > in shouldReduceRegisterPressure()
699 Register VReg1 = MRI->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass); in generateLoadForNewConst()
701 BuildMI(*MF, MI->getDebugLoc(), get(PPC::ADDIStocHA8), VReg1) in generateLoadForNewConst()
702 .addReg(PPC::X2) in generateLoadForNewConst()
711 LoadOpcode = PPC::DFLOADf32; in generateLoadForNewConst()
713 LoadOpcode = PPC::DFLOADf64; in generateLoadForNewConst()
1022 .addReg(PPC::ZERO8); in reassociateFMA()
1059 case PPC::EXTSW: in isCoalescableExtInstr()
1060 case PPC::EXTSW_32: in isCoalescableExtInstr()
1061 case PPC::EXTSW_32_64: in isCoalescableExtInstr()
1064 SubIdx = PPC::sub_32; in isCoalescableExtInstr()
1097 case PPC::LI: in isReallyTriviallyReMaterializable()
1098 case PPC::LI8: in isReallyTriviallyReMaterializable()
1099 case PPC::PLI: in isReallyTriviallyReMaterializable()
1100 case PPC::PLI8: in isReallyTriviallyReMaterializable()
1101 case PPC::LIS: in isReallyTriviallyReMaterializable()
1102 case PPC::LIS8: in isReallyTriviallyReMaterializable()
1103 case PPC::ADDIStocHA: in isReallyTriviallyReMaterializable()
1104 case PPC::ADDIStocHA8: in isReallyTriviallyReMaterializable()
1105 case PPC::ADDItocL: in isReallyTriviallyReMaterializable()
1106 case PPC::LOAD_STACK_GUARD: in isReallyTriviallyReMaterializable()
1107 case PPC::XXLXORz: in isReallyTriviallyReMaterializable()
1108 case PPC::XXLXORspz: in isReallyTriviallyReMaterializable()
1109 case PPC::XXLXORdpz: in isReallyTriviallyReMaterializable()
1110 case PPC::XXLEQVOnes: in isReallyTriviallyReMaterializable()
1111 case PPC::XXSPLTI32DX: in isReallyTriviallyReMaterializable()
1112 case PPC::XXSPLTIW: in isReallyTriviallyReMaterializable()
1113 case PPC::XXSPLTIDP: in isReallyTriviallyReMaterializable()
1114 case PPC::V_SET0B: in isReallyTriviallyReMaterializable()
1115 case PPC::V_SET0H: in isReallyTriviallyReMaterializable()
1116 case PPC::V_SET0: in isReallyTriviallyReMaterializable()
1117 case PPC::V_SETALLONESB: in isReallyTriviallyReMaterializable()
1118 case PPC::V_SETALLONESH: in isReallyTriviallyReMaterializable()
1119 case PPC::V_SETALLONES: in isReallyTriviallyReMaterializable()
1120 case PPC::CRSET: in isReallyTriviallyReMaterializable()
1121 case PPC::CRUNSET: in isReallyTriviallyReMaterializable()
1122 case PPC::XXSETACCZ: in isReallyTriviallyReMaterializable()
1150 if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMI_rec) in commuteInstructionImpl()
1235 int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode()); in findCommutedOpIndices()
1251 default: Opcode = PPC::NOP; break; in insertNoop()
1252 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break; in insertNoop()
1253 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break; in insertNoop()
1254 …case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling mod… in insertNoop()
1256 case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break; in insertNoop()
1266 Nop.setOpcode(PPC::NOP); in getNop()
1291 if (I->getOpcode() == PPC::B && in analyzeBranch()
1307 if (LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1312 } else if (LastInst.getOpcode() == PPC::BCC) { in analyzeBranch()
1320 } else if (LastInst.getOpcode() == PPC::BC) { in analyzeBranch()
1325 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in analyzeBranch()
1328 } else if (LastInst.getOpcode() == PPC::BCn) { in analyzeBranch()
1333 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); in analyzeBranch()
1336 } else if (LastInst.getOpcode() == PPC::BDNZ8 || in analyzeBranch()
1337 LastInst.getOpcode() == PPC::BDNZ) { in analyzeBranch()
1344 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1347 } else if (LastInst.getOpcode() == PPC::BDZ8 || in analyzeBranch()
1348 LastInst.getOpcode() == PPC::BDZ) { in analyzeBranch()
1355 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1372 if (SecondLastInst.getOpcode() == PPC::BCC && in analyzeBranch()
1373 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1382 } else if (SecondLastInst.getOpcode() == PPC::BC && in analyzeBranch()
1383 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1388 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in analyzeBranch()
1392 } else if (SecondLastInst.getOpcode() == PPC::BCn && in analyzeBranch()
1393 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1398 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); in analyzeBranch()
1402 } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 || in analyzeBranch()
1403 SecondLastInst.getOpcode() == PPC::BDNZ) && in analyzeBranch()
1404 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1412 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1416 } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 || in analyzeBranch()
1417 SecondLastInst.getOpcode() == PPC::BDZ) && in analyzeBranch()
1418 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1426 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1434 if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1456 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC && in removeBranch()
1457 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn && in removeBranch()
1458 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && in removeBranch()
1459 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) in removeBranch()
1469 if (I->getOpcode() != PPC::BCC && in removeBranch()
1470 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn && in removeBranch()
1471 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && in removeBranch()
1472 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) in removeBranch()
1497 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); in insertBranch()
1498 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in insertBranch()
1500 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in insertBranch()
1501 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in insertBranch()
1502 else if (Cond[0].getImm() == PPC::PRED_BIT_SET) in insertBranch()
1503 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB); in insertBranch()
1504 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) in insertBranch()
1505 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB); in insertBranch()
1507 BuildMI(&MBB, DL, get(PPC::BCC)) in insertBranch()
1515 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in insertBranch()
1517 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in insertBranch()
1518 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in insertBranch()
1519 else if (Cond[0].getImm() == PPC::PRED_BIT_SET) in insertBranch()
1520 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB); in insertBranch()
1521 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) in insertBranch()
1522 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB); in insertBranch()
1524 BuildMI(&MBB, DL, get(PPC::BCC)) in insertBranch()
1528 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); in insertBranch()
1543 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in canInsertSelect()
1559 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1560 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
1561 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1562 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
1590 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || in insertSelect()
1591 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); in insertSelect()
1593 PPC::GPRCRegClass.hasSubClassEq(RC) || in insertSelect()
1594 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && in insertSelect()
1597 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL; in insertSelect()
1598 auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm()); in insertSelect()
1603 case PPC::PRED_EQ: in insertSelect()
1604 case PPC::PRED_EQ_MINUS: in insertSelect()
1605 case PPC::PRED_EQ_PLUS: in insertSelect()
1606 SubIdx = PPC::sub_eq; SwapOps = false; break; in insertSelect()
1607 case PPC::PRED_NE: in insertSelect()
1608 case PPC::PRED_NE_MINUS: in insertSelect()
1609 case PPC::PRED_NE_PLUS: in insertSelect()
1610 SubIdx = PPC::sub_eq; SwapOps = true; break; in insertSelect()
1611 case PPC::PRED_LT: in insertSelect()
1612 case PPC::PRED_LT_MINUS: in insertSelect()
1613 case PPC::PRED_LT_PLUS: in insertSelect()
1614 SubIdx = PPC::sub_lt; SwapOps = false; break; in insertSelect()
1615 case PPC::PRED_GE: in insertSelect()
1616 case PPC::PRED_GE_MINUS: in insertSelect()
1617 case PPC::PRED_GE_PLUS: in insertSelect()
1618 SubIdx = PPC::sub_lt; SwapOps = true; break; in insertSelect()
1619 case PPC::PRED_GT: in insertSelect()
1620 case PPC::PRED_GT_MINUS: in insertSelect()
1621 case PPC::PRED_GT_PLUS: in insertSelect()
1622 SubIdx = PPC::sub_gt; SwapOps = false; break; in insertSelect()
1623 case PPC::PRED_LE: in insertSelect()
1624 case PPC::PRED_LE_MINUS: in insertSelect()
1625 case PPC::PRED_LE_PLUS: in insertSelect()
1626 SubIdx = PPC::sub_gt; SwapOps = true; break; in insertSelect()
1627 case PPC::PRED_UN: in insertSelect()
1628 case PPC::PRED_UN_MINUS: in insertSelect()
1629 case PPC::PRED_UN_PLUS: in insertSelect()
1630 SubIdx = PPC::sub_un; SwapOps = false; break; in insertSelect()
1631 case PPC::PRED_NU: in insertSelect()
1632 case PPC::PRED_NU_MINUS: in insertSelect()
1633 case PPC::PRED_NU_PLUS: in insertSelect()
1634 SubIdx = PPC::sub_un; SwapOps = true; break; in insertSelect()
1635 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break; in insertSelect()
1636 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break; in insertSelect()
1645 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
1646 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
1648 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
1649 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass; in insertSelect()
1663 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT || in getCRBitValue()
1664 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT || in getCRBitValue()
1665 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT || in getCRBitValue()
1666 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT) in getCRBitValue()
1668 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT || in getCRBitValue()
1669 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT || in getCRBitValue()
1670 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT || in getCRBitValue()
1671 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT) in getCRBitValue()
1673 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ || in getCRBitValue()
1674 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ || in getCRBitValue()
1675 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ || in getCRBitValue()
1676 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ) in getCRBitValue()
1678 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN || in getCRBitValue()
1679 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN || in getCRBitValue()
1680 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN || in getCRBitValue()
1681 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN) in getCRBitValue()
1695 if (PPC::F8RCRegClass.contains(DestReg) && in copyPhysReg()
1696 PPC::VSRCRegClass.contains(SrcReg)) { in copyPhysReg()
1698 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass); in copyPhysReg()
1704 } else if (PPC::F8RCRegClass.contains(SrcReg) && in copyPhysReg()
1705 PPC::VSRCRegClass.contains(DestReg)) { in copyPhysReg()
1707 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass); in copyPhysReg()
1716 if (PPC::CRBITRCRegClass.contains(SrcReg) && in copyPhysReg()
1717 PPC::GPRCRegClass.contains(DestReg)) { in copyPhysReg()
1719 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg); in copyPhysReg()
1723 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg) in copyPhysReg()
1729 } else if (PPC::CRRCRegClass.contains(SrcReg) && in copyPhysReg()
1730 (PPC::G8RCRegClass.contains(DestReg) || in copyPhysReg()
1731 PPC::GPRCRegClass.contains(DestReg))) { in copyPhysReg()
1732 bool Is64Bit = PPC::G8RCRegClass.contains(DestReg); in copyPhysReg()
1733 unsigned MvCode = Is64Bit ? PPC::MFOCRF8 : PPC::MFOCRF; in copyPhysReg()
1734 unsigned ShCode = Is64Bit ? PPC::RLWINM8 : PPC::RLWINM; in copyPhysReg()
1747 } else if (PPC::G8RCRegClass.contains(SrcReg) && in copyPhysReg()
1748 PPC::VSFRCRegClass.contains(DestReg)) { in copyPhysReg()
1751 BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg); in copyPhysReg()
1755 } else if (PPC::VSFRCRegClass.contains(SrcReg) && in copyPhysReg()
1756 PPC::G8RCRegClass.contains(DestReg)) { in copyPhysReg()
1759 BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg); in copyPhysReg()
1762 } else if (PPC::SPERCRegClass.contains(SrcReg) && in copyPhysReg()
1763 PPC::GPRCRegClass.contains(DestReg)) { in copyPhysReg()
1764 BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg); in copyPhysReg()
1767 } else if (PPC::GPRCRegClass.contains(SrcReg) && in copyPhysReg()
1768 PPC::SPERCRegClass.contains(DestReg)) { in copyPhysReg()
1769 BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg); in copyPhysReg()
1775 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1776 Opc = PPC::OR; in copyPhysReg()
1777 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1778 Opc = PPC::OR8; in copyPhysReg()
1779 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1780 Opc = PPC::FMR; in copyPhysReg()
1781 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1782 Opc = PPC::MCRF; in copyPhysReg()
1783 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1784 Opc = PPC::VOR; in copyPhysReg()
1785 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1794 Opc = PPC::XXLOR; in copyPhysReg()
1795 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) || in copyPhysReg()
1796 PPC::VSSRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1797 Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf; in copyPhysReg()
1799 PPC::VSRpRCRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
1800 if (SrcReg > PPC::VSRp15) in copyPhysReg()
1801 SrcReg = PPC::V0 + (SrcReg - PPC::VSRp16) * 2; in copyPhysReg()
1803 SrcReg = PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2; in copyPhysReg()
1804 if (DestReg > PPC::VSRp15) in copyPhysReg()
1805 DestReg = PPC::V0 + (DestReg - PPC::VSRp16) * 2; in copyPhysReg()
1807 DestReg = PPC::VSL0 + (DestReg - PPC::VSRp0) * 2; in copyPhysReg()
1808 BuildMI(MBB, I, DL, get(PPC::XXLOR), DestReg). in copyPhysReg()
1810 BuildMI(MBB, I, DL, get(PPC::XXLOR), DestReg + 1). in copyPhysReg()
1814 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1815 Opc = PPC::CROR; in copyPhysReg()
1816 else if (PPC::SPERCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1817 Opc = PPC::EVOR; in copyPhysReg()
1818 else if ((PPC::ACCRCRegClass.contains(DestReg) || in copyPhysReg()
1819 PPC::UACCRCRegClass.contains(DestReg)) && in copyPhysReg()
1820 (PPC::ACCRCRegClass.contains(SrcReg) || in copyPhysReg()
1821 PPC::UACCRCRegClass.contains(SrcReg))) { in copyPhysReg()
1827 bool DestPrimed = PPC::ACCRCRegClass.contains(DestReg); in copyPhysReg()
1828 bool SrcPrimed = PPC::ACCRCRegClass.contains(SrcReg); in copyPhysReg()
1830 PPC::VSL0 + (SrcReg - (SrcPrimed ? PPC::ACC0 : PPC::UACC0)) * 4; in copyPhysReg()
1832 PPC::VSL0 + (DestReg - (DestPrimed ? PPC::ACC0 : PPC::UACC0)) * 4; in copyPhysReg()
1834 BuildMI(MBB, I, DL, get(PPC::XXMFACC), SrcReg).addReg(SrcReg); in copyPhysReg()
1836 BuildMI(MBB, I, DL, get(PPC::XXLOR), VSLDestReg + Idx) in copyPhysReg()
1840 BuildMI(MBB, I, DL, get(PPC::XXMTACC), DestReg).addReg(DestReg); in copyPhysReg()
1842 BuildMI(MBB, I, DL, get(PPC::XXMTACC), SrcReg).addReg(SrcReg); in copyPhysReg()
1844 } else if (PPC::G8pRCRegClass.contains(DestReg) && in copyPhysReg()
1845 PPC::G8pRCRegClass.contains(SrcReg)) { in copyPhysReg()
1847 unsigned DestRegIdx = DestReg - PPC::G8p0; in copyPhysReg()
1848 MCRegister DestRegSub0 = PPC::X0 + 2 * DestRegIdx; in copyPhysReg()
1849 MCRegister DestRegSub1 = PPC::X0 + 2 * DestRegIdx + 1; in copyPhysReg()
1850 unsigned SrcRegIdx = SrcReg - PPC::G8p0; in copyPhysReg()
1851 MCRegister SrcRegSub0 = PPC::X0 + 2 * SrcRegIdx; in copyPhysReg()
1852 MCRegister SrcRegSub1 = PPC::X0 + 2 * SrcRegIdx + 1; in copyPhysReg()
1853 BuildMI(MBB, I, DL, get(PPC::OR8), DestRegSub0) in copyPhysReg()
1856 BuildMI(MBB, I, DL, get(PPC::OR8), DestRegSub1) in copyPhysReg()
1874 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1875 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in getSpillIndex()
1877 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1878 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) { in getSpillIndex()
1880 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1882 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1884 } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1886 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1888 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1890 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1892 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1894 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1896 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1898 } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1900 } else if (PPC::ACCRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1904 } else if (PPC::UACCRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1908 } else if (PPC::VSRpRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1912 } else if (PPC::G8pRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1946 if (PPC::CRRCRegClass.hasSubClassEq(RC) || in StoreRegToStackSlot()
1947 PPC::CRBITRCRegClass.hasSubClassEq(RC)) in StoreRegToStackSlot()
2001 if (PPC::CRRCRegClass.hasSubClassEq(RC) || in LoadRegFromStackSlot()
2002 PPC::CRBITRCRegClass.hasSubClassEq(RC)) in LoadRegFromStackSlot()
2054 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR) in reverseBranchCondition()
2058 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); in reverseBranchCondition()
2069 if (DefOpc != PPC::LI && DefOpc != PPC::LI8) in onlyFoldImmediate()
2105 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID && in onlyFoldImmediate()
2106 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID) in onlyFoldImmediate()
2119 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2121 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in onlyFoldImmediate()
2122 PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2142 if (MI.definesRegister(PPC::CTR) || MI.definesRegister(PPC::CTR8)) in MBBDefinesCTR()
2179 if (MI.getOpcode() == PPC::MFFS || MI.getOpcode() == PPC::MTFSF) in isSchedulingBoundary()
2187 if (OpC == PPC::BLR || OpC == PPC::BLR8) { in PredicateInstruction()
2188 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { in PredicateInstruction()
2190 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) in PredicateInstruction()
2191 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR))); in PredicateInstruction()
2196 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
2197 MI.setDesc(get(PPC::BCLR)); in PredicateInstruction()
2199 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
2200 MI.setDesc(get(PPC::BCLRn)); in PredicateInstruction()
2203 MI.setDesc(get(PPC::BCCLR)); in PredicateInstruction()
2210 } else if (OpC == PPC::B) { in PredicateInstruction()
2211 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { in PredicateInstruction()
2213 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) in PredicateInstruction()
2214 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ))); in PredicateInstruction()
2219 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
2223 MI.setDesc(get(PPC::BC)); in PredicateInstruction()
2227 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
2231 MI.setDesc(get(PPC::BCn)); in PredicateInstruction()
2239 MI.setDesc(get(PPC::BCC)); in PredicateInstruction()
2247 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL || in PredicateInstruction()
2248 OpC == PPC::BCTRL8 || OpC == PPC::BCTRL_RM || in PredicateInstruction()
2249 OpC == PPC::BCTRL8_RM) { in PredicateInstruction()
2250 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) in PredicateInstruction()
2253 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8 || in PredicateInstruction()
2254 OpC == PPC::BCTRL_RM || OpC == PPC::BCTRL8_RM; in PredicateInstruction()
2257 if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
2258 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) in PredicateInstruction()
2259 : (setLR ? PPC::BCCTRL : PPC::BCCTR))); in PredicateInstruction()
2261 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
2262 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) in PredicateInstruction()
2263 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn))); in PredicateInstruction()
2266 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) in PredicateInstruction()
2267 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR))); in PredicateInstruction()
2276 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::Implicit) in PredicateInstruction()
2277 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::ImplicitDefine); in PredicateInstruction()
2278 if (OpC == PPC::BCTRL_RM || OpC == PPC::BCTRL8_RM) in PredicateInstruction()
2280 .addReg(PPC::RM, RegState::ImplicitDefine); in PredicateInstruction()
2293 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR) in SubsumesPredicate()
2295 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR) in SubsumesPredicate()
2302 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm(); in SubsumesPredicate()
2303 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm(); in SubsumesPredicate()
2309 if (P1 == PPC::PRED_LE && in SubsumesPredicate()
2310 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ)) in SubsumesPredicate()
2312 if (P1 == PPC::PRED_GE && in SubsumesPredicate()
2313 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ)) in SubsumesPredicate()
2329 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass, in ClobbersPredicate()
2330 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass }; in ClobbersPredicate()
2361 case PPC::CMPWI: in analyzeCompare()
2362 case PPC::CMPLWI: in analyzeCompare()
2363 case PPC::CMPDI: in analyzeCompare()
2364 case PPC::CMPLDI: in analyzeCompare()
2370 case PPC::CMPW: in analyzeCompare()
2371 case PPC::CMPLW: in analyzeCompare()
2372 case PPC::CMPD: in analyzeCompare()
2373 case PPC::CMPLD: in analyzeCompare()
2374 case PPC::FCMPUS: in analyzeCompare()
2375 case PPC::FCMPUD: in analyzeCompare()
2396 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD) in optimizeCompareInstr()
2409 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW; in optimizeCompareInstr()
2410 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW; in optimizeCompareInstr()
2411 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD; in optimizeCompareInstr()
2451 if (UseMI->getOpcode() == PPC::BCC) { in optimizeCompareInstr()
2452 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
2453 unsigned PredCond = PPC::getPredicateCondition(Pred); in optimizeCompareInstr()
2455 if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE) in optimizeCompareInstr()
2457 } else if (UseMI->getOpcode() == PPC::ISEL || in optimizeCompareInstr()
2458 UseMI->getOpcode() == PPC::ISEL8) { in optimizeCompareInstr()
2460 if (SubIdx != PPC::sub_eq) in optimizeCompareInstr()
2485 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate; in optimizeCompareInstr()
2514 if (UseMI->getOpcode() != PPC::BCC) in optimizeCompareInstr()
2517 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
2518 unsigned PredCond = PPC::getPredicateCondition(Pred); in optimizeCompareInstr()
2519 unsigned PredHint = PPC::getPredicateHint(Pred); in optimizeCompareInstr()
2524 if (Immed == -1 && PredCond == PPC::PRED_GT) in optimizeCompareInstr()
2527 Pred = PPC::getPredicate(PPC::PRED_GE, PredHint); in optimizeCompareInstr()
2528 else if (Immed == -1 && PredCond == PPC::PRED_LE) in optimizeCompareInstr()
2530 Pred = PPC::getPredicate(PPC::PRED_LT, PredHint); in optimizeCompareInstr()
2531 else if (Immed == 1 && PredCond == PPC::PRED_LT) in optimizeCompareInstr()
2533 Pred = PPC::getPredicate(PPC::PRED_LE, PredHint); in optimizeCompareInstr()
2534 else if (Immed == 1 && PredCond == PPC::PRED_GE) in optimizeCompareInstr()
2536 Pred = PPC::getPredicate(PPC::PRED_GT, PredHint); in optimizeCompareInstr()
2553 if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) || in optimizeCompareInstr()
2554 Instr.readsRegister(PPC::CR0, TRI))) in optimizeCompareInstr()
2563 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW || in optimizeCompareInstr()
2564 OpC == PPC::CMPD || OpC == PPC::CMPLD) && in optimizeCompareInstr()
2565 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) && in optimizeCompareInstr()
2588 if (MIOpC == PPC::ANDI_rec || MIOpC == PPC::ANDI8_rec || in optimizeCompareInstr()
2589 MIOpC == PPC::ANDIS_rec || MIOpC == PPC::ANDIS8_rec) in optimizeCompareInstr()
2592 NewOpC = PPC::getRecordFormOpcode(MIOpC); in optimizeCompareInstr()
2593 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1) in optimizeCompareInstr()
2610 if (!equalityOnly && (NewOpC == PPC::SUBF_rec || NewOpC == PPC::SUBF8_rec) && in optimizeCompareInstr()
2635 if (UseMI->getOpcode() == PPC::BCC) { in optimizeCompareInstr()
2636 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
2637 unsigned PredCond = PPC::getPredicateCondition(Pred); in optimizeCompareInstr()
2639 PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) && in optimizeCompareInstr()
2643 PPC::getSwappedPredicate(Pred))); in optimizeCompareInstr()
2644 } else if (UseMI->getOpcode() == PPC::ISEL || in optimizeCompareInstr()
2645 UseMI->getOpcode() == PPC::ISEL8) { in optimizeCompareInstr()
2647 assert((!equalityOnly || NewSubReg == PPC::sub_eq) && in optimizeCompareInstr()
2650 if (NewSubReg == PPC::sub_lt) in optimizeCompareInstr()
2651 NewSubReg = PPC::sub_gt; in optimizeCompareInstr()
2652 else if (NewSubReg == PPC::sub_gt) in optimizeCompareInstr()
2653 NewSubReg = PPC::sub_lt; in optimizeCompareInstr()
2672 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0); in optimizeCompareInstr()
2676 MI->clearRegisterDeads(PPC::CR0); in optimizeCompareInstr()
2688 if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) { in optimizeCompareInstr()
2703 NewOpC = MIOpC == PPC::RLWINM in optimizeCompareInstr()
2704 ? (MBInLoHWord ? PPC::ANDI_rec : PPC::ANDIS_rec) in optimizeCompareInstr()
2705 : (MBInLoHWord ? PPC::ANDI8_rec : PPC::ANDIS8_rec); in optimizeCompareInstr()
2713 NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDIS_rec : PPC::ANDIS8_rec; in optimizeCompareInstr()
2722 } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) { in optimizeCompareInstr()
2726 NewOpC = PPC::ANDI8_rec; in optimizeCompareInstr()
2749 assert(MI->definesRegister(PPC::CR0) && in optimizeCompareInstr()
2801 case PPC::STD: in isClusterableLdStOpcPair()
2802 case PPC::STFD: in isClusterableLdStOpcPair()
2803 case PPC::STXSD: in isClusterableLdStOpcPair()
2804 case PPC::DFSTOREf64: in isClusterableLdStOpcPair()
2809 case PPC::STW: in isClusterableLdStOpcPair()
2810 case PPC::STW8: in isClusterableLdStOpcPair()
2811 return SecondOpc == PPC::STW || SecondOpc == PPC::STW8; in isClusterableLdStOpcPair()
2876 if (Opcode == PPC::INLINEASM || Opcode == PPC::INLINEASM_BR) { in getInstSizeInBytes()
2940 case PPC::DFLOADf32: in expandVSXMemPseudo()
2941 UpperOpcode = PPC::LXSSP; in expandVSXMemPseudo()
2942 LowerOpcode = PPC::LFS; in expandVSXMemPseudo()
2944 case PPC::DFLOADf64: in expandVSXMemPseudo()
2945 UpperOpcode = PPC::LXSD; in expandVSXMemPseudo()
2946 LowerOpcode = PPC::LFD; in expandVSXMemPseudo()
2948 case PPC::DFSTOREf32: in expandVSXMemPseudo()
2949 UpperOpcode = PPC::STXSSP; in expandVSXMemPseudo()
2950 LowerOpcode = PPC::STFS; in expandVSXMemPseudo()
2952 case PPC::DFSTOREf64: in expandVSXMemPseudo()
2953 UpperOpcode = PPC::STXSD; in expandVSXMemPseudo()
2954 LowerOpcode = PPC::STFD; in expandVSXMemPseudo()
2956 case PPC::XFLOADf32: in expandVSXMemPseudo()
2957 UpperOpcode = PPC::LXSSPX; in expandVSXMemPseudo()
2958 LowerOpcode = PPC::LFSX; in expandVSXMemPseudo()
2960 case PPC::XFLOADf64: in expandVSXMemPseudo()
2961 UpperOpcode = PPC::LXSDX; in expandVSXMemPseudo()
2962 LowerOpcode = PPC::LFDX; in expandVSXMemPseudo()
2964 case PPC::XFSTOREf32: in expandVSXMemPseudo()
2965 UpperOpcode = PPC::STXSSPX; in expandVSXMemPseudo()
2966 LowerOpcode = PPC::STFSX; in expandVSXMemPseudo()
2968 case PPC::XFSTOREf64: in expandVSXMemPseudo()
2969 UpperOpcode = PPC::STXSDX; in expandVSXMemPseudo()
2970 LowerOpcode = PPC::STFDX; in expandVSXMemPseudo()
2972 case PPC::LIWAX: in expandVSXMemPseudo()
2973 UpperOpcode = PPC::LXSIWAX; in expandVSXMemPseudo()
2974 LowerOpcode = PPC::LFIWAX; in expandVSXMemPseudo()
2976 case PPC::LIWZX: in expandVSXMemPseudo()
2977 UpperOpcode = PPC::LXSIWZX; in expandVSXMemPseudo()
2978 LowerOpcode = PPC::LFIWZX; in expandVSXMemPseudo()
2980 case PPC::STIWX: in expandVSXMemPseudo()
2981 UpperOpcode = PPC::STXSIWX; in expandVSXMemPseudo()
2982 LowerOpcode = PPC::STFIWX; in expandVSXMemPseudo()
2990 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || in expandVSXMemPseudo()
2991 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31)) in expandVSXMemPseudo()
3008 case PPC::BUILD_UACC: { in expandPostRAPseudo()
3011 if (ACC - PPC::ACC0 != UACC - PPC::UACC0) { in expandPostRAPseudo()
3012 MCRegister SrcVSR = PPC::VSL0 + (UACC - PPC::UACC0) * 4; in expandPostRAPseudo()
3013 MCRegister DstVSR = PPC::VSL0 + (ACC - PPC::ACC0) * 4; in expandPostRAPseudo()
3018 BuildMI(MBB, MI, DL, get(PPC::XXLOR), DstVSR + VecNo) in expandPostRAPseudo()
3027 case PPC::KILL_PAIR: { in expandPostRAPseudo()
3028 MI.setDesc(get(PPC::UNENCODED_NOP)); in expandPostRAPseudo()
3037 const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2; in expandPostRAPseudo()
3038 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ)); in expandPostRAPseudo()
3044 case PPC::DFLOADf32: in expandPostRAPseudo()
3045 case PPC::DFLOADf64: in expandPostRAPseudo()
3046 case PPC::DFSTOREf32: in expandPostRAPseudo()
3047 case PPC::DFSTOREf64: { in expandPostRAPseudo()
3055 case PPC::XFLOADf32: in expandPostRAPseudo()
3056 case PPC::XFSTOREf32: in expandPostRAPseudo()
3057 case PPC::LIWAX: in expandPostRAPseudo()
3058 case PPC::LIWZX: in expandPostRAPseudo()
3059 case PPC::STIWX: { in expandPostRAPseudo()
3066 case PPC::XFLOADf64: in expandPostRAPseudo()
3067 case PPC::XFSTOREf64: { in expandPostRAPseudo()
3074 case PPC::SPILLTOVSR_LD: { in expandPostRAPseudo()
3076 if (PPC::VSFRCRegClass.contains(TargetReg)) { in expandPostRAPseudo()
3077 MI.setDesc(get(PPC::DFLOADf64)); in expandPostRAPseudo()
3081 MI.setDesc(get(PPC::LD)); in expandPostRAPseudo()
3084 case PPC::SPILLTOVSR_ST: { in expandPostRAPseudo()
3086 if (PPC::VSFRCRegClass.contains(SrcReg)) { in expandPostRAPseudo()
3088 MI.setDesc(get(PPC::DFSTOREf64)); in expandPostRAPseudo()
3092 MI.setDesc(get(PPC::STD)); in expandPostRAPseudo()
3096 case PPC::SPILLTOVSR_LDX: { in expandPostRAPseudo()
3098 if (PPC::VSFRCRegClass.contains(TargetReg)) in expandPostRAPseudo()
3099 MI.setDesc(get(PPC::LXSDX)); in expandPostRAPseudo()
3101 MI.setDesc(get(PPC::LDX)); in expandPostRAPseudo()
3104 case PPC::SPILLTOVSR_STX: { in expandPostRAPseudo()
3106 if (PPC::VSFRCRegClass.contains(SrcReg)) { in expandPostRAPseudo()
3108 MI.setDesc(get(PPC::STXSDX)); in expandPostRAPseudo()
3111 MI.setDesc(get(PPC::STDX)); in expandPostRAPseudo()
3117 case PPC::CFENCE8: { in expandPostRAPseudo()
3119 BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val); in expandPostRAPseudo()
3120 BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP)) in expandPostRAPseudo()
3121 .addImm(PPC::PRED_NE_MINUS) in expandPostRAPseudo()
3122 .addReg(PPC::CR7) in expandPostRAPseudo()
3124 MI.setDesc(get(PPC::ISYNC)); in expandPostRAPseudo()
3140 if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) { in selectReg()
3143 case PPC::sub_lt: in selectReg()
3145 case PPC::sub_gt: in selectReg()
3147 case PPC::sub_eq: in selectReg()
3152 else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) { in selectReg()
3155 case PPC::sub_lt: in selectReg()
3157 case PPC::sub_gt: in selectReg()
3159 case PPC::sub_eq: in selectReg()
3163 return PPC::NoRegister; in selectReg()
3206 MI.setDesc(get(LII.Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec)); in replaceInstrWithLI()
3209 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine); in replaceInstrWithLI()
3213 MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI)); in replaceInstrWithLI()
3248 BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LI8 : PPC::LI), Reg).addImm(Imm); in materializeImmPostRA()
3250 BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LIS8 : PPC::LIS), Reg) in materializeImmPostRA()
3253 BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::ORI8 : PPC::ORI), Reg) in materializeImmPostRA()
3259 BuildMI(MBB, MBBI, DL, get(PPC::LIS8), Reg).addImm(Imm >> 48); in materializeImmPostRA()
3261 BuildMI(MBB, MBBI, DL, get(PPC::ORI8), Reg) in materializeImmPostRA()
3264 BuildMI(MBB, MBBI, DL, get(PPC::RLDICR), Reg) in materializeImmPostRA()
3268 BuildMI(MBB, MBBI, DL, get(PPC::ORIS8), Reg) in materializeImmPostRA()
3272 BuildMI(MBB, MBBI, DL, get(PPC::ORI8), Reg) in materializeImmPostRA()
3299 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8 || in getForwardingDefMI()
3300 DefMI->getOpcode() == PPC::ADDI || in getForwardingDefMI()
3301 DefMI->getOpcode() == PPC::ADDI8) { in getForwardingDefMI()
3307 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) in getForwardingDefMI()
3319 Opc == PPC::CMPWI || Opc == PPC::CMPLWI || Opc == PPC::CMPDI || in getForwardingDefMI()
3320 Opc == PPC::CMPLDI || Opc == PPC::ADDI || Opc == PPC::ADDI8 || in getForwardingDefMI()
3321 Opc == PPC::ORI || Opc == PPC::ORI8 || Opc == PPC::XORI || in getForwardingDefMI()
3322 Opc == PPC::XORI8 || Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec || in getForwardingDefMI()
3323 Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 || in getForwardingDefMI()
3324 Opc == PPC::RLWINM || Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8 || in getForwardingDefMI()
3325 Opc == PPC::RLWINM8_rec; in getForwardingDefMI()
3333 if ((Opc == PPC::OR || Opc == PPC::OR8) && in getForwardingDefMI()
3350 case PPC::LI: in getForwardingDefMI()
3351 case PPC::LI8: in getForwardingDefMI()
3352 case PPC::ADDItocL: in getForwardingDefMI()
3353 case PPC::ADDI: in getForwardingDefMI()
3354 case PPC::ADDI8: in getForwardingDefMI()
3558 (ScaleReg == PPC::R0 || ScaleReg == PPC::X0)) in foldFrameOffset()
3601 if (Opc != PPC::ADDI && Opc != PPC::ADDI8) in isADDIInstrEligibleForFolding()
3617 return Opc == PPC::ADD4 || Opc == PPC::ADD8; in isADDInstrEligibleForFolding()
3634 if (XFormOpcode == PPC::INSTRUCTION_LIST_END) in isImmInstrEligibleForFolding()
3729 PPC::INSTRUCTION_LIST_END && in convertToImmediateForm()
3767 if (SrcMI->getOpcode() != PPC::RLWINM && in combineRLWINM()
3768 SrcMI->getOpcode() != PPC::RLWINM_rec && in combineRLWINM()
3769 SrcMI->getOpcode() != PPC::RLWINM8 && in combineRLWINM()
3770 SrcMI->getOpcode() != PPC::RLWINM8_rec) in combineRLWINM()
3827 (MI.getOpcode() == PPC::RLWINM8 || MI.getOpcode() == PPC::RLWINM8_rec); in combineRLWINM()
3832 if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8) { in combineRLWINM()
3838 MI.setDesc(get(Is64Bit ? PPC::LI8 : PPC::LI)); in combineRLWINM()
3844 MI.setDesc(get(Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec)); in combineRLWINM()
3911 case PPC::ADD4: in instrHasImmForm()
3912 case PPC::ADD8: in instrHasImmForm()
3918 III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8; in instrHasImmForm()
3920 case PPC::ADDC: in instrHasImmForm()
3921 case PPC::ADDC8: in instrHasImmForm()
3927 III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8; in instrHasImmForm()
3929 case PPC::ADDC_rec: in instrHasImmForm()
3935 III.ImmOpcode = PPC::ADDIC_rec; in instrHasImmForm()
3937 case PPC::SUBFC: in instrHasImmForm()
3938 case PPC::SUBFC8: in instrHasImmForm()
3943 III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8; in instrHasImmForm()
3945 case PPC::CMPW: in instrHasImmForm()
3946 case PPC::CMPD: in instrHasImmForm()
3951 III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI; in instrHasImmForm()
3953 case PPC::CMPLW: in instrHasImmForm()
3954 case PPC::CMPLD: in instrHasImmForm()
3959 III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI; in instrHasImmForm()
3961 case PPC::AND_rec: in instrHasImmForm()
3962 case PPC::AND8_rec: in instrHasImmForm()
3963 case PPC::OR: in instrHasImmForm()
3964 case PPC::OR8: in instrHasImmForm()
3965 case PPC::XOR: in instrHasImmForm()
3966 case PPC::XOR8: in instrHasImmForm()
3973 case PPC::AND_rec: in instrHasImmForm()
3974 III.ImmOpcode = PPC::ANDI_rec; in instrHasImmForm()
3976 case PPC::AND8_rec: in instrHasImmForm()
3977 III.ImmOpcode = PPC::ANDI8_rec; in instrHasImmForm()
3979 case PPC::OR: III.ImmOpcode = PPC::ORI; break; in instrHasImmForm()
3980 case PPC::OR8: III.ImmOpcode = PPC::ORI8; break; in instrHasImmForm()
3981 case PPC::XOR: III.ImmOpcode = PPC::XORI; break; in instrHasImmForm()
3982 case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break; in instrHasImmForm()
3985 case PPC::RLWNM: in instrHasImmForm()
3986 case PPC::RLWNM8: in instrHasImmForm()
3987 case PPC::RLWNM_rec: in instrHasImmForm()
3988 case PPC::RLWNM8_rec: in instrHasImmForm()
3989 case PPC::SLW: in instrHasImmForm()
3990 case PPC::SLW8: in instrHasImmForm()
3991 case PPC::SLW_rec: in instrHasImmForm()
3992 case PPC::SLW8_rec: in instrHasImmForm()
3993 case PPC::SRW: in instrHasImmForm()
3994 case PPC::SRW8: in instrHasImmForm()
3995 case PPC::SRW_rec: in instrHasImmForm()
3996 case PPC::SRW8_rec: in instrHasImmForm()
3997 case PPC::SRAW: in instrHasImmForm()
3998 case PPC::SRAW_rec: in instrHasImmForm()
4008 if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 || Opc == PPC::RLWNM_rec || in instrHasImmForm()
4009 Opc == PPC::RLWNM8_rec) in instrHasImmForm()
4015 case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break; in instrHasImmForm()
4016 case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break; in instrHasImmForm()
4017 case PPC::RLWNM_rec: in instrHasImmForm()
4018 III.ImmOpcode = PPC::RLWINM_rec; in instrHasImmForm()
4020 case PPC::RLWNM8_rec: in instrHasImmForm()
4021 III.ImmOpcode = PPC::RLWINM8_rec; in instrHasImmForm()
4023 case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break; in instrHasImmForm()
4024 case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break; in instrHasImmForm()
4025 case PPC::SLW_rec: in instrHasImmForm()
4026 III.ImmOpcode = PPC::RLWINM_rec; in instrHasImmForm()
4028 case PPC::SLW8_rec: in instrHasImmForm()
4029 III.ImmOpcode = PPC::RLWINM8_rec; in instrHasImmForm()
4031 case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break; in instrHasImmForm()
4032 case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break; in instrHasImmForm()
4033 case PPC::SRW_rec: in instrHasImmForm()
4034 III.ImmOpcode = PPC::RLWINM_rec; in instrHasImmForm()
4036 case PPC::SRW8_rec: in instrHasImmForm()
4037 III.ImmOpcode = PPC::RLWINM8_rec; in instrHasImmForm()
4039 case PPC::SRAW: in instrHasImmForm()
4042 III.ImmOpcode = PPC::SRAWI; in instrHasImmForm()
4044 case PPC::SRAW_rec: in instrHasImmForm()
4047 III.ImmOpcode = PPC::SRAWI_rec; in instrHasImmForm()
4051 case PPC::RLDCL: in instrHasImmForm()
4052 case PPC::RLDCL_rec: in instrHasImmForm()
4053 case PPC::RLDCR: in instrHasImmForm()
4054 case PPC::RLDCR_rec: in instrHasImmForm()
4055 case PPC::SLD: in instrHasImmForm()
4056 case PPC::SLD_rec: in instrHasImmForm()
4057 case PPC::SRD: in instrHasImmForm()
4058 case PPC::SRD_rec: in instrHasImmForm()
4059 case PPC::SRAD: in instrHasImmForm()
4060 case PPC::SRAD_rec: in instrHasImmForm()
4070 if (Opc == PPC::RLDCL || Opc == PPC::RLDCL_rec || Opc == PPC::RLDCR || in instrHasImmForm()
4071 Opc == PPC::RLDCR_rec) in instrHasImmForm()
4077 case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break; in instrHasImmForm()
4078 case PPC::RLDCL_rec: in instrHasImmForm()
4079 III.ImmOpcode = PPC::RLDICL_rec; in instrHasImmForm()
4081 case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break; in instrHasImmForm()
4082 case PPC::RLDCR_rec: in instrHasImmForm()
4083 III.ImmOpcode = PPC::RLDICR_rec; in instrHasImmForm()
4085 case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break; in instrHasImmForm()
4086 case PPC::SLD_rec: in instrHasImmForm()
4087 III.ImmOpcode = PPC::RLDICR_rec; in instrHasImmForm()
4089 case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break; in instrHasImmForm()
4090 case PPC::SRD_rec: in instrHasImmForm()
4091 III.ImmOpcode = PPC::RLDICL_rec; in instrHasImmForm()
4093 case PPC::SRAD: in instrHasImmForm()
4096 III.ImmOpcode = PPC::SRADI; in instrHasImmForm()
4098 case PPC::SRAD_rec: in instrHasImmForm()
4101 III.ImmOpcode = PPC::SRADI_rec; in instrHasImmForm()
4106 case PPC::LBZX: in instrHasImmForm()
4107 case PPC::LBZX8: in instrHasImmForm()
4108 case PPC::LHZX: in instrHasImmForm()
4109 case PPC::LHZX8: in instrHasImmForm()
4110 case PPC::LHAX: in instrHasImmForm()
4111 case PPC::LHAX8: in instrHasImmForm()
4112 case PPC::LWZX: in instrHasImmForm()
4113 case PPC::LWZX8: in instrHasImmForm()
4114 case PPC::LWAX: in instrHasImmForm()
4115 case PPC::LDX: in instrHasImmForm()
4116 case PPC::LFSX: in instrHasImmForm()
4117 case PPC::LFDX: in instrHasImmForm()
4118 case PPC::STBX: in instrHasImmForm()
4119 case PPC::STBX8: in instrHasImmForm()
4120 case PPC::STHX: in instrHasImmForm()
4121 case PPC::STHX8: in instrHasImmForm()
4122 case PPC::STWX: in instrHasImmForm()
4123 case PPC::STWX8: in instrHasImmForm()
4124 case PPC::STDX: in instrHasImmForm()
4125 case PPC::STFSX: in instrHasImmForm()
4126 case PPC::STFDX: in instrHasImmForm()
4136 case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break; in instrHasImmForm()
4137 case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break; in instrHasImmForm()
4138 case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break; in instrHasImmForm()
4139 case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break; in instrHasImmForm()
4140 case PPC::LHAX: III.ImmOpcode = PPC::LHA; break; in instrHasImmForm()
4141 case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break; in instrHasImmForm()
4142 case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break; in instrHasImmForm()
4143 case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break; in instrHasImmForm()
4144 case PPC::LWAX: in instrHasImmForm()
4145 III.ImmOpcode = PPC::LWA; in instrHasImmForm()
4148 case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break; in instrHasImmForm()
4149 case PPC::LFSX: III.ImmOpcode = PPC::LFS; break; in instrHasImmForm()
4150 case PPC::LFDX: III.ImmOpcode = PPC::LFD; break; in instrHasImmForm()
4151 case PPC::STBX: III.ImmOpcode = PPC::STB; break; in instrHasImmForm()
4152 case PPC::STBX8: III.ImmOpcode = PPC::STB8; break; in instrHasImmForm()
4153 case PPC::STHX: III.ImmOpcode = PPC::STH; break; in instrHasImmForm()
4154 case PPC::STHX8: III.ImmOpcode = PPC::STH8; break; in instrHasImmForm()
4155 case PPC::STWX: III.ImmOpcode = PPC::STW; break; in instrHasImmForm()
4156 case PPC::STWX8: III.ImmOpcode = PPC::STW8; break; in instrHasImmForm()
4157 case PPC::STDX: in instrHasImmForm()
4158 III.ImmOpcode = PPC::STD; in instrHasImmForm()
4161 case PPC::STFSX: III.ImmOpcode = PPC::STFS; break; in instrHasImmForm()
4162 case PPC::STFDX: III.ImmOpcode = PPC::STFD; break; in instrHasImmForm()
4165 case PPC::LBZUX: in instrHasImmForm()
4166 case PPC::LBZUX8: in instrHasImmForm()
4167 case PPC::LHZUX: in instrHasImmForm()
4168 case PPC::LHZUX8: in instrHasImmForm()
4169 case PPC::LHAUX: in instrHasImmForm()
4170 case PPC::LHAUX8: in instrHasImmForm()
4171 case PPC::LWZUX: in instrHasImmForm()
4172 case PPC::LWZUX8: in instrHasImmForm()
4173 case PPC::LDUX: in instrHasImmForm()
4174 case PPC::LFSUX: in instrHasImmForm()
4175 case PPC::LFDUX: in instrHasImmForm()
4176 case PPC::STBUX: in instrHasImmForm()
4177 case PPC::STBUX8: in instrHasImmForm()
4178 case PPC::STHUX: in instrHasImmForm()
4179 case PPC::STHUX8: in instrHasImmForm()
4180 case PPC::STWUX: in instrHasImmForm()
4181 case PPC::STWUX8: in instrHasImmForm()
4182 case PPC::STDUX: in instrHasImmForm()
4183 case PPC::STFSUX: in instrHasImmForm()
4184 case PPC::STFDUX: in instrHasImmForm()
4194 case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break; in instrHasImmForm()
4195 case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break; in instrHasImmForm()
4196 case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break; in instrHasImmForm()
4197 case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break; in instrHasImmForm()
4198 case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break; in instrHasImmForm()
4199 case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break; in instrHasImmForm()
4200 case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break; in instrHasImmForm()
4201 case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break; in instrHasImmForm()
4202 case PPC::LDUX: in instrHasImmForm()
4203 III.ImmOpcode = PPC::LDU; in instrHasImmForm()
4206 case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break; in instrHasImmForm()
4207 case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break; in instrHasImmForm()
4208 case PPC::STBUX: III.ImmOpcode = PPC::STBU; break; in instrHasImmForm()
4209 case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break; in instrHasImmForm()
4210 case PPC::STHUX: III.ImmOpcode = PPC::STHU; break; in instrHasImmForm()
4211 case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break; in instrHasImmForm()
4212 case PPC::STWUX: III.ImmOpcode = PPC::STWU; break; in instrHasImmForm()
4213 case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break; in instrHasImmForm()
4214 case PPC::STDUX: in instrHasImmForm()
4215 III.ImmOpcode = PPC::STDU; in instrHasImmForm()
4218 case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break; in instrHasImmForm()
4219 case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break; in instrHasImmForm()
4226 case PPC::LXVX: in instrHasImmForm()
4227 case PPC::LXSSPX: in instrHasImmForm()
4228 case PPC::LXSDX: in instrHasImmForm()
4229 case PPC::STXVX: in instrHasImmForm()
4230 case PPC::STXSSPX: in instrHasImmForm()
4231 case PPC::STXSDX: in instrHasImmForm()
4232 case PPC::XFLOADf32: in instrHasImmForm()
4233 case PPC::XFLOADf64: in instrHasImmForm()
4234 case PPC::XFSTOREf32: in instrHasImmForm()
4235 case PPC::XFSTOREf64: in instrHasImmForm()
4248 case PPC::LXVX: in instrHasImmForm()
4249 III.ImmOpcode = PPC::LXV; in instrHasImmForm()
4252 case PPC::LXSSPX: in instrHasImmForm()
4255 III.ImmOpcode = PPC::LXSSP; in instrHasImmForm()
4257 III.ImmOpcode = PPC::LFS; in instrHasImmForm()
4263 case PPC::XFLOADf32: in instrHasImmForm()
4264 III.ImmOpcode = PPC::DFLOADf32; in instrHasImmForm()
4266 case PPC::LXSDX: in instrHasImmForm()
4269 III.ImmOpcode = PPC::LXSD; in instrHasImmForm()
4271 III.ImmOpcode = PPC::LFD; in instrHasImmForm()
4277 case PPC::XFLOADf64: in instrHasImmForm()
4278 III.ImmOpcode = PPC::DFLOADf64; in instrHasImmForm()
4280 case PPC::STXVX: in instrHasImmForm()
4281 III.ImmOpcode = PPC::STXV; in instrHasImmForm()
4284 case PPC::STXSSPX: in instrHasImmForm()
4287 III.ImmOpcode = PPC::STXSSP; in instrHasImmForm()
4289 III.ImmOpcode = PPC::STFS; in instrHasImmForm()
4295 case PPC::XFSTOREf32: in instrHasImmForm()
4296 III.ImmOpcode = PPC::DFSTOREf32; in instrHasImmForm()
4298 case PPC::STXSDX: in instrHasImmForm()
4301 III.ImmOpcode = PPC::STXSD; in instrHasImmForm()
4303 III.ImmOpcode = PPC::STFD; in instrHasImmForm()
4309 case PPC::XFSTOREf64: in instrHasImmForm()
4310 III.ImmOpcode = PPC::DFSTOREf64; in instrHasImmForm()
4384 if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO && in isUseMIElgibleForForwarding()
4385 MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8) in isUseMIElgibleForForwarding()
4402 if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8) in isDefMIElgibleForForwarding()
4465 if (DefMI.getOpcode() == PPC::ADDItocL) { in isImmElgibleForForwarding()
4514 if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) || in simplifyToLI()
4542 case PPC::CMPWI: in simplifyToLI()
4543 case PPC::CMPLWI: in simplifyToLI()
4544 case PPC::CMPDI: in simplifyToLI()
4545 case PPC::CMPLDI: { in simplifyToLI()
4563 if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8) in simplifyToLI()
4570 if (RegToCopy == PPC::NoRegister) in simplifyToLI()
4573 if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) { in simplifyToLI()
4574 CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI)); in simplifyToLI()
4585 CompareUseMI.setDesc(get(PPC::COPY)); in simplifyToLI()
4602 case PPC::ADDI: in simplifyToLI()
4603 case PPC::ADDI8: { in simplifyToLI()
4608 Is64BitLI = Opc == PPC::ADDI8; in simplifyToLI()
4614 case PPC::SUBFIC: in simplifyToLI()
4615 case PPC::SUBFIC8: { in simplifyToLI()
4622 Is64BitLI = Opc == PPC::SUBFIC8; in simplifyToLI()
4628 case PPC::RLDICL: in simplifyToLI()
4629 case PPC::RLDICL_rec: in simplifyToLI()
4630 case PPC::RLDICL_32: in simplifyToLI()
4631 case PPC::RLDICL_32_64: { in simplifyToLI()
4635 APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec) ? 64 : 32, in simplifyToLI()
4644 (Opc == PPC::RLDICL_rec && isUInt<16>(InVal.getSExtValue()))) { in simplifyToLI()
4646 Is64BitLI = Opc != PPC::RLDICL_32; in simplifyToLI()
4648 SetCR = Opc == PPC::RLDICL_rec; in simplifyToLI()
4653 case PPC::RLWINM: in simplifyToLI()
4654 case PPC::RLWINM8: in simplifyToLI()
4655 case PPC::RLWINM_rec: in simplifyToLI()
4656 case PPC::RLWINM8_rec: { in simplifyToLI()
4668 ValueFits |= ((Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec) && in simplifyToLI()
4672 Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8_rec; in simplifyToLI()
4674 SetCR = Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec; in simplifyToLI()
4679 case PPC::ORI: in simplifyToLI()
4680 case PPC::ORI8: in simplifyToLI()
4681 case PPC::XORI: in simplifyToLI()
4682 case PPC::XORI8: { in simplifyToLI()
4685 if (Opc == PPC::ORI || Opc == PPC::ORI8) in simplifyToLI()
4691 Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8; in simplifyToLI()
4769 assert((XFormOpcode != PPC::INSTRUCTION_LIST_END) && in transformToNewImmFormFedByAdd()
4921 if (DefMI.getOpcode() == PPC::ADDItocL) in transformToImmFormFedByAdd()
4973 if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) || in transformToImmFormFedByLI()
5009 if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) && in transformToImmFormFedByLI()
5012 if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) && in transformToImmFormFedByLI()
5023 bool SpecialShift32 = Opc == PPC::SLW || Opc == PPC::SLW_rec || in transformToImmFormFedByLI()
5024 Opc == PPC::SRW || Opc == PPC::SRW_rec || in transformToImmFormFedByLI()
5025 Opc == PPC::SLW8 || Opc == PPC::SLW8_rec || in transformToImmFormFedByLI()
5026 Opc == PPC::SRW8 || Opc == PPC::SRW8_rec; in transformToImmFormFedByLI()
5027 bool SpecialShift64 = Opc == PPC::SLD || Opc == PPC::SLD_rec || in transformToImmFormFedByLI()
5028 Opc == PPC::SRD || Opc == PPC::SRD_rec; in transformToImmFormFedByLI()
5029 bool SetCR = Opc == PPC::SLW_rec || Opc == PPC::SRW_rec || in transformToImmFormFedByLI()
5030 Opc == PPC::SLD_rec || Opc == PPC::SRD_rec; in transformToImmFormFedByLI()
5031 bool RightShift = Opc == PPC::SRW || Opc == PPC::SRW_rec || Opc == PPC::SRD || in transformToImmFormFedByLI()
5032 Opc == PPC::SRD_rec; in transformToImmFormFedByLI()
5055 MI.setDesc(get(PPC::COPY)); in transformToImmFormFedByLI()
5104 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ? in transformToImmFormFedByLI()
5105 &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass; in transformToImmFormFedByLI()
5122 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass) in updatedRC()
5123 return &PPC::VSRCRegClass; in updatedRC()
5128 return PPC::getRecordFormOpcode(Opcode); in getRecordFormOpcode()
5136 if (Opcode == PPC::LI || Opcode == PPC::LI8 || Opcode == PPC::LIS || in isSignExtendingOp()
5137 Opcode == PPC::LIS8 || Opcode == PPC::SRAW || Opcode == PPC::SRAW_rec || in isSignExtendingOp()
5138 Opcode == PPC::SRAWI || Opcode == PPC::SRAWI_rec || Opcode == PPC::LWA || in isSignExtendingOp()
5139 Opcode == PPC::LWAX || Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 || in isSignExtendingOp()
5140 Opcode == PPC::LHA || Opcode == PPC::LHAX || Opcode == PPC::LHA8 || in isSignExtendingOp()
5141 Opcode == PPC::LHAX8 || Opcode == PPC::LBZ || Opcode == PPC::LBZX || in isSignExtendingOp()
5142 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || Opcode == PPC::LBZU || in isSignExtendingOp()
5143 Opcode == PPC::LBZUX || Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 || in isSignExtendingOp()
5144 Opcode == PPC::LHZ || Opcode == PPC::LHZX || Opcode == PPC::LHZ8 || in isSignExtendingOp()
5145 Opcode == PPC::LHZX8 || Opcode == PPC::LHZU || Opcode == PPC::LHZUX || in isSignExtendingOp()
5146 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 || Opcode == PPC::EXTSB || in isSignExtendingOp()
5147 Opcode == PPC::EXTSB_rec || Opcode == PPC::EXTSH || in isSignExtendingOp()
5148 Opcode == PPC::EXTSH_rec || Opcode == PPC::EXTSB8 || in isSignExtendingOp()
5149 Opcode == PPC::EXTSH8 || Opcode == PPC::EXTSW || in isSignExtendingOp()
5150 Opcode == PPC::EXTSW_rec || Opcode == PPC::SETB || Opcode == PPC::SETB8 || in isSignExtendingOp()
5151 Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 || in isSignExtendingOp()
5152 Opcode == PPC::EXTSB8_32_64) in isSignExtendingOp()
5155 if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33) in isSignExtendingOp()
5158 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || in isSignExtendingOp()
5159 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec) && in isSignExtendingOp()
5173 if (Opcode == PPC::LI || Opcode == PPC::LI8 || in isZeroExtendingOp()
5174 Opcode == PPC::LIS || Opcode == PPC::LIS8) { in isZeroExtendingOp()
5182 if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec || in isZeroExtendingOp()
5183 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec || in isZeroExtendingOp()
5184 Opcode == PPC::RLDICL_32_64) && in isZeroExtendingOp()
5188 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) && in isZeroExtendingOp()
5193 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || in isZeroExtendingOp()
5194 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec || in isZeroExtendingOp()
5195 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && in isZeroExtendingOp()
5200 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec || in isZeroExtendingOp()
5201 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec || in isZeroExtendingOp()
5202 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 || in isZeroExtendingOp()
5203 Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec || in isZeroExtendingOp()
5204 Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec || in isZeroExtendingOp()
5205 Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW || Opcode == PPC::SLW || in isZeroExtendingOp()
5206 Opcode == PPC::SLW_rec || Opcode == PPC::SRW || Opcode == PPC::SRW_rec || in isZeroExtendingOp()
5207 Opcode == PPC::SLW8 || Opcode == PPC::SRW8 || Opcode == PPC::SLWI || in isZeroExtendingOp()
5208 Opcode == PPC::SLWI_rec || Opcode == PPC::SRWI || in isZeroExtendingOp()
5209 Opcode == PPC::SRWI_rec || Opcode == PPC::LWZ || Opcode == PPC::LWZX || in isZeroExtendingOp()
5210 Opcode == PPC::LWZU || Opcode == PPC::LWZUX || Opcode == PPC::LWBRX || in isZeroExtendingOp()
5211 Opcode == PPC::LHBRX || Opcode == PPC::LHZ || Opcode == PPC::LHZX || in isZeroExtendingOp()
5212 Opcode == PPC::LHZU || Opcode == PPC::LHZUX || Opcode == PPC::LBZ || in isZeroExtendingOp()
5213 Opcode == PPC::LBZX || Opcode == PPC::LBZU || Opcode == PPC::LBZUX || in isZeroExtendingOp()
5214 Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 || Opcode == PPC::LWZU8 || in isZeroExtendingOp()
5215 Opcode == PPC::LWZUX8 || Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 || in isZeroExtendingOp()
5216 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || Opcode == PPC::LHZU8 || in isZeroExtendingOp()
5217 Opcode == PPC::LHZUX8 || Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || in isZeroExtendingOp()
5218 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 || in isZeroExtendingOp()
5219 Opcode == PPC::ANDI_rec || Opcode == PPC::ANDIS_rec || in isZeroExtendingOp()
5220 Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWI_rec || in isZeroExtendingOp()
5221 Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWI_rec || in isZeroExtendingOp()
5222 Opcode == PPC::MFVSRWZ) in isZeroExtendingOp()
5236 Register SPReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in isTOCSaveMI()
5260 case PPC::COPY: { in isSignOrZeroExtended()
5282 if (SrcReg == PPC::X3) { in isSignOrZeroExtended()
5287 (--II)->getOpcode() == PPC::ADJCALLSTACKUP) { in isSignOrZeroExtended()
5315 case PPC::ANDI_rec: in isSignOrZeroExtended()
5316 case PPC::ANDIS_rec: in isSignOrZeroExtended()
5317 case PPC::ORI: in isSignOrZeroExtended()
5318 case PPC::ORIS: in isSignOrZeroExtended()
5319 case PPC::XORI: in isSignOrZeroExtended()
5320 case PPC::XORIS: in isSignOrZeroExtended()
5321 case PPC::ANDI8_rec: in isSignOrZeroExtended()
5322 case PPC::ANDIS8_rec: in isSignOrZeroExtended()
5323 case PPC::ORI8: in isSignOrZeroExtended()
5324 case PPC::ORIS8: in isSignOrZeroExtended()
5325 case PPC::XORI8: in isSignOrZeroExtended()
5326 case PPC::XORIS8: { in isSignOrZeroExtended()
5341 case PPC::OR: in isSignOrZeroExtended()
5342 case PPC::OR8: in isSignOrZeroExtended()
5343 case PPC::ISEL: in isSignOrZeroExtended()
5344 case PPC::PHI: { in isSignOrZeroExtended()
5351 if (MI.getOpcode() == PPC::PHI) { in isSignOrZeroExtended()
5375 case PPC::AND: in isSignOrZeroExtended()
5376 case PPC::AND8: { in isSignOrZeroExtended()
5409 return (Opcode == (Subtarget.isPPC64() ? PPC::BDNZ8 : PPC::BDNZ)); in isBDNZ()
5427 if (LoopCount->getOpcode() == PPC::LI8 || LoopCount->getOpcode() == PPC::LI) in PPCPipelinerLoopInfo()
5446 MF->getSubtarget<PPCSubtarget>().isPPC64() ? PPC::CTR8 : PPC::CTR, in createTripCountGreaterCondition()
5462 if (LoopCount->getOpcode() == PPC::LI8 || in adjustTripCount()
5463 LoopCount->getOpcode() == PPC::LI) { in adjustTripCount()
5506 unsigned LOOPi = (Subtarget.isPPC64() ? PPC::MTCTR8loop : PPC::MTCTRloop); in findLoopInstr()