Lines Matching refs:isPPC64
162 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering() local
163 setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4)); in PPCTargetLowering()
245 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
248 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
251 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
255 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
258 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
262 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
265 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
269 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
272 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
458 if (Subtarget.hasP9Vector() && Subtarget.isPPC64()) in PPCTargetLowering()
538 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
683 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) { in PPCTargetLowering()
984 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
1276 setOperationAction(ISD::SELECT_CC, MVT::i64, isPPC64 ? Custom : Expand); in PPCTargetLowering()
1321 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom); in PPCTargetLowering()
1323 if (!isPPC64) { in PPCTargetLowering()
1342 if (!isPPC64) { in PPCTargetLowering()
1351 if (!isPPC64) in PPCTargetLowering()
1358 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1); in PPCTargetLowering()
1589 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4); in getByValTypeAlignment()
2801 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegImm()
2908 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegRegOnly()
3112 const bool Is64Bit = Subtarget.isPPC64(); in getTOCEntry()
3176 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) in isJumpTableRelative()
3183 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBase()
3200 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBaseExpr()
3335 bool is64bit = Subtarget.isPPC64(); in LowerGlobalTLSAddressLinux()
3586 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); in LowerVAARG()
3677 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"); in LowerVACOPY()
3758 bool isPPC64 = (PtrVT == MVT::i64); in LowerINIT_TRAMPOLINE() local
3768 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl, in LowerINIT_TRAMPOLINE()
3769 isPPC64 ? MVT::i64 : MVT::i32); in LowerINIT_TRAMPOLINE()
3792 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) { in LowerVASTART()
5006 bool isPPC64 = Subtarget.isPPC64(); in EmitTailCallStoreFPAndRetAddr() local
5007 int SlotSize = isPPC64 ? 8 : 4; in EmitTailCallStoreFPAndRetAddr()
5011 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in EmitTailCallStoreFPAndRetAddr()
5022 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, in CalculateTailCallArgDest() argument
5028 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in CalculateTailCallArgDest()
5045 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
5072 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, in LowerMemOpCallTo() argument
5079 if (isPPC64) in LowerMemOpCallTo()
5089 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, in LowerMemOpCallTo()
5437 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall()
5438 const unsigned Alignment = Subtarget.isPPC64() ? 8 : 4; in prepareDescriptorIndirectCall()
5487 const bool IsPPC64 = Subtarget.isPPC64(); in buildCallOperands()
5652 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) in LowerCall()
5703 if (Subtarget.isPPC64()) in LowerCall()
6588 const bool IsPPC64 = Subtarget.isPPC64(); in CC_AIX()
6930 const bool IsPPC64 = Subtarget.isPPC64(); in LowerFormalArguments_AIX()
7245 const bool IsPPC64 = Subtarget.isPPC64(); in LowerCall_AIX()
7509 const MVT PtrVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in LowerCall_AIX()
7640 bool isPPC64 = Subtarget.isPPC64(); in LowerSTACKRESTORE() local
7641 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; in LowerSTACKRESTORE()
7661 bool isPPC64 = Subtarget.isPPC64(); in getReturnAddrFrameIndex() local
7674 RASI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, LROffset, false); in getReturnAddrFrameIndex()
7684 bool isPPC64 = Subtarget.isPPC64(); in getFramePointerFrameIndex() local
7697 FPSI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); in getFramePointerFrameIndex()
7730 bool isPPC64 = Subtarget.isPPC64(); in LowerEH_DWARF_CFA() local
7733 int FI = MF.getFrameInfo().CreateFixedObject(isPPC64 ? 8 : 4, 0, false); in LowerEH_DWARF_CFA()
8241 if (Subtarget.hasDirectMove() && Subtarget.isPPC64()) in LowerFP_TO_INT()
8532 Subtarget.isPPC64() && Subtarget.hasFPCVT()) in LowerINT_TO_FP()
8713 assert(Subtarget.isPPC64() && in LowerINT_TO_FP()
9305 if (Subtarget.hasVSX() && Subtarget.isPPC64() && in LowerBUILD_VECTOR()
10487 if (Subtarget.isPPC64()) in LowerINTRINSIC_WO_CHAIN()
10684 assert(Subtarget.isPPC64() && "Only 64-bit is supported for now."); in LowerINTRINSIC_VOID()
10707 if (!Subtarget.isPPC64()) in LowerBSWAP()
10864 if ((VT == MVT::v2i64 || VT == MVT::v2f64) && !Subtarget.isPPC64()) in LowerINSERT_VECTOR_ELT()
11280 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64()) in ReplaceNodeResults()
11359 if (isa<LoadInst>(Inst) && Subtarget.isPPC64()) in emitTrailingFence()
11576 bool is64bit = Subtarget.isPPC64(); in EmitPartwordAtomicBinary()
11844 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in emitEHSjLjSetJmp()
11846 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP; in emitEHSjLjSetJmp()
11849 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW)) in emitEHSjLjSetJmp()
11872 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg); in emitEHSjLjSetJmp()
11875 if (Subtarget.isPPC64()) { in emitEHSjLjSetJmp()
12038 const bool isPPC64 = Subtarget.isPPC64(); in emitProbedAlloca() local
12079 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1; in emitProbedAlloca()
12080 Register FinalStackPtr = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12081 Register FramePointer = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12082 Register ActualNegSizeReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12090 isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_64 : PPC::PREPARE_PROBED_ALLOCA_32; in emitProbedAlloca()
12096 ProbeOpc = isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 in emitProbedAlloca()
12105 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::ADD8 : PPC::ADD4), in emitProbedAlloca()
12113 Register ScratchReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12115 Register TempReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12116 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS), TempReg) in emitProbedAlloca()
12118 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::ORI8 : PPC::ORI), in emitProbedAlloca()
12123 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LI8 : PPC::LI), ScratchReg) in emitProbedAlloca()
12128 Register Div = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12129 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::DIVD : PPC::DIVW), Div) in emitProbedAlloca()
12132 Register Mul = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12133 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::MULLD : PPC::MULLW), Mul) in emitProbedAlloca()
12136 Register NegMod = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12137 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::SUBF8 : PPC::SUBF), NegMod) in emitProbedAlloca()
12140 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg) in emitProbedAlloca()
12149 BuildMI(TestMBB, DL, TII->get(isPPC64 ? PPC::CMPD : PPC::CMPW), CmpResult) in emitProbedAlloca()
12163 BuildMI(BlockMBB, DL, TII->get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg) in emitProbedAlloca()
12174 MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12176 TII->get(isPPC64 ? PPC::DYNAREAOFFSET8 : PPC::DYNAREAOFFSET), in emitProbedAlloca()
12180 BuildMI(TailMBB, DL, TII->get(isPPC64 ? PPC::ADD8 : PPC::ADD4), DstReg) in emitProbedAlloca()
12582 bool is64bit = Subtarget.isPPC64(); in EmitInstrWithCustomInserter()
13710 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64()))) in DAGCombineExtBoolTrunc()
15177 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) { in PerformDAGCombine()
15212 if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && in PerformDAGCombine()
15605 Subtarget.isPPC64() && N->getValueType(0) == MVT::i64; in PerformDAGCombine()
15852 if (VT == MVT::i64 && !Subtarget.isPPC64()) in BuildSDIVPow2()
16083 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
16087 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
16183 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && in getRegForInlineAsmConstraint()
16344 bool isPPC64 = Subtarget.isPPC64(); in LowerRETURNADDR() local
16356 isPPC64 ? MVT::i64 : MVT::i32); in LowerRETURNADDR()
16378 bool isPPC64 = PtrVT == MVT::i64; in LowerFRAMEADDR() local
16384 FrameReg = isPPC64 ? PPC::X1 : PPC::R1; in LowerFRAMEADDR()
16386 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP; in LowerFRAMEADDR()
16400 bool isPPC64 = Subtarget.isPPC64(); in getRegisterByName() local
16402 bool is64Bit = isPPC64 && VT == LLT::scalar(64); in getRegisterByName()
16408 .Case("r2", isPPC64 ? Register() : PPC::R2) in getRegisterByName()
16586 if (Subtarget.isPPC64()) { in getOptimalMemOpType()
16625 (Subtarget.isPPC64() && MemVT == MVT::i32)) && in isZExtFree()
16807 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3; in getExceptionPointerRegister()
16812 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4; in getExceptionSelectorRegister()
17006 if (!Subtarget.isISA3_0() || !Subtarget.isPPC64() || in combineSHL()
17050 if (!Subtarget.isPPC64()) in combineADDToADDZE()
17802 Disp = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectForceXFormMode()
18023 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()
18079 Disp = FI ? DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()
18102 return Subtarget.isPPC64() && in shouldInlineQuadwordAtomics()