Lines Matching refs:FV
7896 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); in LowerSELECT_CC() local
7907 return DAG.getSelectCC(dl, Z, Zero, TV, FV, ISD::SETNE); in LowerSELECT_CC()
7919 if (Subtarget.hasP9Vector() && LHS == TV && RHS == FV) { in LowerSELECT_CC()
7947 std::swap(TV, FV); in LowerSELECT_CC()
7952 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
7956 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV); in LowerSELECT_CC()
7959 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt in LowerSELECT_CC()
7965 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
7968 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt in LowerSELECT_CC()
7975 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); in LowerSELECT_CC()
7982 std::swap(TV, FV); in LowerSELECT_CC()
7988 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
7992 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV); in LowerSELECT_CC()
7998 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
8004 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
8010 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
8016 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()