Lines Matching refs:RBReg
1659 unsigned RBReg = SPReg; in emitEpilogue() local
1702 BuildMI(MBB, MBBI, dl, OrInst, RBReg). in emitEpilogue()
1713 RBReg = FPReg; in emitEpilogue()
1715 BuildMI(MBB, MBBI, dl, AddImmInst, RBReg) in emitEpilogue()
1720 .addReg(RBReg) in emitEpilogue()
1748 RBReg = FPReg; in emitEpilogue()
1750 BuildMI(MBB, StackUpdateLoc, dl, LoadInst, RBReg) in emitEpilogue()
1755 assert(RBReg != ScratchReg && "Should have avoided ScratchReg"); in emitEpilogue()
1779 if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) { in emitEpilogue()
1782 .addReg(RBReg); in emitEpilogue()
1787 assert(RBReg == SPReg && "Should be using SP as a base register"); in emitEpilogue()
1790 .addReg(RBReg); in emitEpilogue()
1796 if (HasRedZone || RBReg == SPReg) in emitEpilogue()
1803 .addReg(RBReg); in emitEpilogue()
1809 .addReg(RBReg); in emitEpilogue()
1814 .addReg(RBReg); in emitEpilogue()
1818 if (RBReg != SPReg || SPAdd != 0) { in emitEpilogue()
1823 .addReg(RBReg) in emitEpilogue()
1824 .addReg(RBReg); in emitEpilogue()
1827 .addReg(RBReg) in emitEpilogue()
1830 assert(RBReg != ScratchReg && "Should be using FP or SP as base register"); in emitEpilogue()
1831 if (RBReg == FPReg) in emitEpilogue()