Lines Matching refs:Cycle

460 // 5 Cycle Restricted DP operation and one 2 cycle ALU operation.
523 // Three Cycle PM operation. Only one PM unit per superslice so we use the whole
633 // 12 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
657 // 23 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
665 // 24 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
682 // 37 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
690 // 58 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
699 // 76 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
708 // 6 Cycle Load uses a single slice.
714 // 5 Cycle Load uses a single slice.
733 // 4 Cycle Load uses a single slice.
761 // 4 Cycle Restricted load uses a single slice but the dispatch for the whole
917 // 5 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
926 // 12 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
940 // 16 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
952 // 24 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
970 // 40 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
1127 // 33 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1133 // 33 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1140 // 36 Cycle DP Instruction.
1147 // 36 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1153 // 36 Cycle DP Vector Instruction.
1160 // 27 Cycle DP Vector Instruction.
1167 // 36 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1174 // 26 Cycle DP Instruction.
1180 // 26 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1186 // 26 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1193 // 33 Cycle DP Instruction. Takes one slice and 1 dispatch.
1199 // 22 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
1205 // 22 Cycle DP Instruction Restricted and Cracked with 2 Cycle ALU.
1212 // 22 Cycle DP Instruction. Takes one slice and 1 dispatch.
1218 // 24 Cycle DP Vector Instruction. Takes one full superslice.
1227 // 33 Cycle DP Vector Instruction. Takes one full superslice.
1281 // 6 Cycle CY operation. Only one CY unit per CPU so we use a whole
1293 // Two Cycle Branch
1326 // Five Cycle Branch with a 2 Cycle ALU Op