Lines Matching refs:MipsSubtarget
62 bool MipsSubtarget::DspWarningPrinted = false;
63 bool MipsSubtarget::MSAWarningPrinted = false;
64 bool MipsSubtarget::VirtWarningPrinted = false;
65 bool MipsSubtarget::CRCWarningPrinted = false;
66 bool MipsSubtarget::GINVWarningPrinted = false;
67 bool MipsSubtarget::MIPS1WarningPrinted = false;
69 void MipsSubtarget::anchor() {} in anchor()
71 MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, in MipsSubtarget() function in MipsSubtarget
225 bool MipsSubtarget::isPositionIndependent() const { in isPositionIndependent()
230 bool MipsSubtarget::enablePostRAScheduler() const { return true; } in enablePostRAScheduler()
232 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { in getCriticalPathRCs()
238 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const { in getOptLevelToEnablePostRAScheduler()
242 MipsSubtarget &
243 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, in initializeSubtargetDependencies()
271 bool MipsSubtarget::useConstantIslands() { in useConstantIslands()
277 Reloc::Model MipsSubtarget::getRelocationModel() const { in getRelocationModel()
281 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); } in isABI_N64()
282 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); } in isABI_N32()
283 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); } in isABI_O32()
284 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); } in getABI()
286 const CallLowering *MipsSubtarget::getCallLowering() const { in getCallLowering()
290 const LegalizerInfo *MipsSubtarget::getLegalizerInfo() const { in getLegalizerInfo()
294 const RegisterBankInfo *MipsSubtarget::getRegBankInfo() const { in getRegBankInfo()
298 InstructionSelector *MipsSubtarget::getInstructionSelector() const { in getInstructionSelector()