Lines Matching refs:rt

16 //  rt      - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
148 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
157   bits<5>  rt;
165   let Inst{20-16} = rt;
186 // MFC instruction class in Mips : <|op|mf|rt|rd|gst|0000|sel|>
189   bits<5> rt;
197   let Inst{20-16} = rt;
205   bits<5>  rt;
212   let Inst{20-16} = rt;
219   bits<5> rt;
225   let Inst{20-16} = rt;
233   bits<5>  rt;
240   let Inst{20-16} = rt;
246   bits<5> rt;
254   let Inst{20-16} = rt;
262   bits<5> rt;
269   let Inst{20-16} = rt;
278   bits<5>  rt;
285   let Inst{20-16} = rt;
315   bits<5> rt;
323   let Inst{20-16} = rt;
352   bits<5> rt;
358   let Inst{20-16} = rt;
367   bits<5> rt;
373   let Inst{20-16} = rt;
377   let rt = rd;
381   bits<5> rt;
388   let Inst{20-16} = rt;
444   bits<5>  rt;
450   let Inst{20-16} = rt;
456   bits<5> rt;
465   let Inst{20-16} = rt;
472   bits<5> rt;
480   let Inst{20-16} = rt;
489   bits<5> rt;
496   let Inst{20-16} = rt;
523   bits<5> rt;
532   let Inst{20-16} = rt;
566   bits<5> rt;
572   let Inst{20-16} = rt;
580   bits<5> rt;
587   let Inst{20-16} = rt;
593   bits<5> rt;
600   let Inst{20-16} = rt;
648 //  Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
654   bits<5> rt;
657   let Inst{20-16} = rt;
711   bits<5> rt;
718   let Inst{20-16} = rt;
724   bits<5> rt;
731   let Inst{20-16} = rt;
820   bits<5> rt;
826   let Inst{20-16} = rt;
871   let Inst{20-16} = 0; // rt = 0