Lines Matching refs:getRegClassFor
1638 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitSignExtendToI32InReg()
1657 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicBinaryPartword()
1660 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicBinaryPartword()
1853 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); in emitAtomicCmpSwap()
1905 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicCmpSwapPartword()
1908 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicCmpSwapPartword()
2537 Register Reg = MF.addLiveIn(RA, getRegClassFor(VT)); in lowerRETURNADDR()
3685 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3764 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); in LowerFormalArguments()
4102 RC = getRegClassFor(VT); in parseRegForInlineAsmConstraint()
4111 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); in parseRegForInlineAsmConstraint()
4114 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); in parseRegForInlineAsmConstraint()
4384 const TargetRegisterClass *RC = getRegClassFor(RegTy); in copyByValRegs()
4503 const TargetRegisterClass *RC = getRegClassFor(RegTy); in writeVarArgRegs()