Lines Matching refs:SDValue

76 bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,  in selectAddrRegImm()
77 SDValue &Offset) const { in selectAddrRegImm()
82 bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base, in selectAddrDefault()
83 SDValue &Offset) const { in selectAddrDefault()
88 bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base, in selectIntAddr()
89 SDValue &Offset) const { in selectIntAddr()
94 bool MipsDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base, in selectIntAddr11MM()
95 SDValue &Offset) const { in selectIntAddr11MM()
100 bool MipsDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base, in selectIntAddr12MM()
101 SDValue &Offset) const { in selectIntAddr12MM()
106 bool MipsDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base, in selectIntAddr16MM()
107 SDValue &Offset) const { in selectIntAddr16MM()
112 bool MipsDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base, in selectIntAddrLSL2MM()
113 SDValue &Offset) const { in selectIntAddrLSL2MM()
118 bool MipsDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base, in selectIntAddrSImm10()
119 SDValue &Offset) const { in selectIntAddrSImm10()
124 bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base, in selectIntAddrSImm10Lsl1()
125 SDValue &Offset) const { in selectIntAddrSImm10Lsl1()
130 bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base, in selectIntAddrSImm10Lsl2()
131 SDValue &Offset) const { in selectIntAddrSImm10Lsl2()
136 bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base, in selectIntAddrSImm10Lsl3()
137 SDValue &Offset) const { in selectIntAddrSImm10Lsl3()
142 bool MipsDAGToDAGISel::selectAddr16(SDValue Addr, SDValue &Base, in selectAddr16()
143 SDValue &Offset) { in selectAddr16()
148 bool MipsDAGToDAGISel::selectAddr16SP(SDValue Addr, SDValue &Base, in selectAddr16SP()
149 SDValue &Offset) { in selectAddr16SP()
160 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const { in selectVSplatUimm1()
165 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const { in selectVSplatUimm2()
170 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const { in selectVSplatUimm3()
175 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const { in selectVSplatUimm4()
180 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const { in selectVSplatUimm5()
185 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const { in selectVSplatUimm6()
190 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const { in selectVSplatUimm8()
195 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const { in selectVSplatSimm5()
200 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const { in selectVSplatUimmPow2()
205 bool MipsDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const { in selectVSplatUimmInvPow2()
210 bool MipsDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const { in selectVSplatMaskL()
215 bool MipsDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const { in selectVSplatMaskR()
229 SDValue X = Node->getOperand(0); in selectVecAddAsVecSubIfProfitable()
230 SDValue C = Node->getOperand(1); in selectVecAddAsVecSubIfProfitable()
255 SDValue NegC = CurDAG->FoldConstantArithmetic( in selectVecAddAsVecSubIfProfitable()
258 SDValue NewNode = CurDAG->getNode(ISD::SUB, DL, VT, X, NegC); in selectVecAddAsVecSubIfProfitable()
311 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, in SelectInlineAsmMemoryOperand()
312 std::vector<SDValue> &OutOps) { in SelectInlineAsmMemoryOperand()