Lines Matching refs:createResultReg
324 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp()
340 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca()
361 Register ResultReg = createResultReg(RC); in materialize32BitInt()
375 Register TmpReg = createResultReg(RC); in materialize32BitInt()
390 Register DestReg = createResultReg(RC); in materializeFP()
396 Register DestReg = createResultReg(RC); in materializeFP()
411 Register DestReg = createResultReg(RC); in materializeGV()
422 Register TempReg = createResultReg(RC); in materializeGV()
433 Register DestReg = createResultReg(RC); in materializeExternalCallSym()
648 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
654 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
666 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
672 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
684 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
690 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
736 Register RegWithZero = createResultReg(&Mips::GPR32RegClass); in emitCmp()
737 Register RegWithOne = createResultReg(&Mips::GPR32RegClass); in emitCmp()
759 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
763 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
767 ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLoad()
773 ResultReg = createResultReg(&Mips::FGR32RegClass); in emitLoad()
779 ResultReg = createResultReg(&Mips::AFGR64RegClass); in emitLoad()
953 ZExtCondReg = createResultReg(&Mips::GPR32RegClass); in selectBranch()
979 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in selectCmp()
1003 Register DestReg = createResultReg(&Mips::AFGR64RegClass); in selectFPExt()
1045 Register ZExtCondReg = createResultReg(&Mips::GPR32RegClass); in selectSelect()
1052 Register ResultReg = createResultReg(RC); in selectSelect()
1053 Register TempReg = createResultReg(RC); in selectSelect()
1080 Register DestReg = createResultReg(&Mips::FGR32RegClass); in selectFPTrunc()
1118 Register DestReg = createResultReg(&Mips::GPR32RegClass); in selectFPToInt()
1119 Register TempReg = createResultReg(&Mips::FGR32RegClass); in selectFPToInt()
1291 Register ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall()
1463 Register ResultReg = createResultReg(Allocation[ArgNo].RC); in fastLowerArguments()
1594 Register DestReg = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1605 R = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1618 Register TempReg = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1626 R = createResultReg(&Mips::GPR32RegClass); in fastLowerIntrinsicCall()
1815 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in selectIntExt()
1836 Register TempReg = createResultReg(&Mips::GPR32RegClass); in emitIntSExt32r1()
1904 unsigned DestReg = createResultReg(&Mips::GPR32RegClass); in emitIntExt()
1940 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in selectDivRem()
1959 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in selectShift()
1971 Register TempReg = createResultReg(&Mips::GPR32RegClass); in selectShift()
2097 Register TempReg = createResultReg(&Mips::GPR32RegClass); in getRegEnsuringSimpleIntegerWidening()
2109 Register DestReg = createResultReg(&Mips::GPR32RegClass); in simplifyAddress()
2126 Register ResultReg = createResultReg(RC); in fastEmitInst_rr()