Lines Matching refs:Decoder
84 const MCDisassembler *Decoder);
88 const MCDisassembler *Decoder);
92 const MCDisassembler *Decoder);
96 const MCDisassembler *Decoder);
100 const MCDisassembler *Decoder);
104 const MCDisassembler *Decoder);
108 const MCDisassembler *Decoder);
112 const MCDisassembler *Decoder);
116 const MCDisassembler *Decoder);
120 const MCDisassembler *Decoder);
124 const MCDisassembler *Decoder);
128 const MCDisassembler *Decoder);
132 const MCDisassembler *Decoder);
136 const MCDisassembler *Decoder);
140 const MCDisassembler *Decoder);
144 const MCDisassembler *Decoder);
148 const MCDisassembler *Decoder);
152 const MCDisassembler *Decoder);
156 const MCDisassembler *Decoder);
160 const MCDisassembler *Decoder);
164 const MCDisassembler *Decoder);
168 const MCDisassembler *Decoder);
172 const MCDisassembler *Decoder);
176 const MCDisassembler *Decoder);
180 const MCDisassembler *Decoder);
184 const MCDisassembler *Decoder);
188 const MCDisassembler *Decoder);
192 const MCDisassembler *Decoder);
196 const MCDisassembler *Decoder);
200 const MCDisassembler *Decoder);
204 const MCDisassembler *Decoder);
210 const MCDisassembler *Decoder);
216 const MCDisassembler *Decoder);
222 const MCDisassembler *Decoder);
228 const MCDisassembler *Decoder);
234 const MCDisassembler *Decoder);
240 const MCDisassembler *Decoder);
243 const MCDisassembler *Decoder);
246 const MCDisassembler *Decoder);
250 const MCDisassembler *Decoder);
253 const MCDisassembler *Decoder);
257 const MCDisassembler *Decoder);
261 const MCDisassembler *Decoder);
265 const MCDisassembler *Decoder);
268 const MCDisassembler *Decoder);
272 const MCDisassembler *Decoder);
275 const MCDisassembler *Decoder);
279 const MCDisassembler *Decoder);
283 const MCDisassembler *Decoder);
287 const MCDisassembler *Decoder);
291 const MCDisassembler *Decoder);
295 const MCDisassembler *Decoder);
299 const MCDisassembler *Decoder);
303 const MCDisassembler *Decoder);
307 const MCDisassembler *Decoder);
310 const MCDisassembler *Decoder);
314 const MCDisassembler *Decoder);
317 const MCDisassembler *Decoder);
320 const MCDisassembler *Decoder);
324 const MCDisassembler *Decoder);
328 const MCDisassembler *Decoder);
332 const MCDisassembler *Decoder);
336 const MCDisassembler *Decoder);
340 const MCDisassembler *Decoder);
344 const MCDisassembler *Decoder);
349 const MCDisassembler *Decoder);
354 const MCDisassembler *Decoder) { in DecodeUImmWithOffset() argument
356 Decoder); in DecodeUImmWithOffset()
362 const MCDisassembler *Decoder);
365 const MCDisassembler *Decoder);
369 const MCDisassembler *Decoder);
373 const MCDisassembler *Decoder);
376 const MCDisassembler *Decoder);
380 const MCDisassembler *Decoder);
384 const MCDisassembler *Decoder);
390 const MCDisassembler *Decoder);
395 const MCDisassembler *Decoder);
399 const MCDisassembler *Decoder);
404 const MCDisassembler *Decoder);
409 const MCDisassembler *Decoder);
414 const MCDisassembler *Decoder);
419 const MCDisassembler *Decoder);
424 const MCDisassembler *Decoder);
429 const MCDisassembler *Decoder);
434 const MCDisassembler *Decoder);
439 const MCDisassembler *Decoder);
444 const MCDisassembler *Decoder);
449 const MCDisassembler *Decoder);
454 const MCDisassembler *Decoder);
459 const MCDisassembler *Decoder);
463 const MCDisassembler *Decoder);
467 const MCDisassembler *Decoder);
471 const MCDisassembler *Decoder);
475 const MCDisassembler *Decoder);
479 const MCDisassembler *Decoder);
483 const MCDisassembler *Decoder);
487 const MCDisassembler *Decoder);
524 const MCDisassembler *Decoder) { in DecodeINSVE_DF() argument
552 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) in DecodeINSVE_DF()
555 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) in DecodeINSVE_DF()
562 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail) in DecodeINSVE_DF()
573 const MCDisassembler *Decoder) { in DecodeDAHIDATIMMR6() argument
576 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
578 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
587 const MCDisassembler *Decoder) { in DecodeDAHIDATI() argument
590 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
592 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
602 const MCDisassembler *Decoder) { in DecodeAddiGroupBranch() argument
628 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
631 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
641 const MCDisassembler *Decoder) { in DecodePOP35GroupBranchMMR6() argument
648 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
650 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
655 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
657 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
662 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
675 const MCDisassembler *Decoder) { in DecodeDaddiGroupBranch() argument
701 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
704 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
714 const MCDisassembler *Decoder) { in DecodePOP37GroupBranchMMR6() argument
721 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
723 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
728 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
730 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
735 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
748 const MCDisassembler *Decoder) { in DecodePOP65GroupBranchMMR6() argument
773 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP65GroupBranchMMR6()
776 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP65GroupBranchMMR6()
787 const MCDisassembler *Decoder) { in DecodePOP75GroupBranchMMR6() argument
812 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP75GroupBranchMMR6()
815 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP75GroupBranchMMR6()
826 const MCDisassembler *Decoder) { in DecodeBlezlGroupBranch() argument
855 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
858 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezlGroupBranch()
869 const MCDisassembler *Decoder) { in DecodeBgtzlGroupBranch() argument
899 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzlGroupBranch()
902 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzlGroupBranch()
913 const MCDisassembler *Decoder) { in DecodeBgtzGroupBranch() argument
947 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzGroupBranch()
951 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBgtzGroupBranch()
962 const MCDisassembler *Decoder) { in DecodeBlezGroupBranch() argument
991 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezGroupBranch()
993 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeBlezGroupBranch()
1005 const MCDisassembler *Decoder) { in DecodeDEXT() argument
1034 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); in DecodeDEXT()
1036 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); in DecodeDEXT()
1047 const MCDisassembler *Decoder) { in DecodeDINS() argument
1077 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); in DecodeDINS()
1079 MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); in DecodeDINS()
1089 const MCDisassembler *Decoder) { in DecodeCRC() argument
1092 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeCRC()
1094 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeCRC()
1096 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeCRC()
1335 const MCDisassembler *Decoder) { in DecodeCPU16RegsRegisterClass() argument
1341 const MCDisassembler *Decoder) { in DecodeGPR64RegisterClass() argument
1345 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); in DecodeGPR64RegisterClass()
1352 const MCDisassembler *Decoder) { in DecodeGPRMM16RegisterClass() argument
1355 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo); in DecodeGPRMM16RegisterClass()
1362 const MCDisassembler *Decoder) { in DecodeGPRMM16ZeroRegisterClass() argument
1365 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo); in DecodeGPRMM16ZeroRegisterClass()
1372 const MCDisassembler *Decoder) { in DecodeGPRMM16MovePRegisterClass() argument
1375 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo); in DecodeGPRMM16MovePRegisterClass()
1382 const MCDisassembler *Decoder) { in DecodeGPR32RegisterClass() argument
1385 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); in DecodeGPR32RegisterClass()
1392 const MCDisassembler *Decoder) { in DecodePtrRegisterClass() argument
1393 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64()) in DecodePtrRegisterClass()
1394 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); in DecodePtrRegisterClass()
1396 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); in DecodePtrRegisterClass()
1401 const MCDisassembler *Decoder) { in DecodeDSPRRegisterClass() argument
1402 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); in DecodeDSPRRegisterClass()
1407 const MCDisassembler *Decoder) { in DecodeFGR64RegisterClass() argument
1411 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); in DecodeFGR64RegisterClass()
1418 const MCDisassembler *Decoder) { in DecodeFGR32RegisterClass() argument
1422 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); in DecodeFGR32RegisterClass()
1429 const MCDisassembler *Decoder) { in DecodeCCRRegisterClass() argument
1432 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); in DecodeCCRRegisterClass()
1439 const MCDisassembler *Decoder) { in DecodeFCCRegisterClass() argument
1442 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); in DecodeFCCRegisterClass()
1449 const MCDisassembler *Decoder) { in DecodeFGRCCRegisterClass() argument
1453 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo); in DecodeFGRCCRegisterClass()
1459 const MCDisassembler *Decoder) { in DecodeMem() argument
1464 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMem()
1465 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMem()
1479 const MCDisassembler *Decoder) { in DecodeMemEVA() argument
1484 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemEVA()
1485 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemEVA()
1499 const MCDisassembler *Decoder) { in DecodeLoadByte15() argument
1504 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeLoadByte15()
1505 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeLoadByte15()
1515 const MCDisassembler *Decoder) { in DecodeCacheOp() argument
1520 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeCacheOp()
1531 const MCDisassembler *Decoder) { in DecodeCacheOpMM() argument
1536 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeCacheOpMM()
1547 const MCDisassembler *Decoder) { in DecodePrefeOpMM() argument
1552 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodePrefeOpMM()
1563 const MCDisassembler *Decoder) { in DecodeCacheeOp_CacheOpR6() argument
1568 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeCacheeOp_CacheOpR6()
1578 const MCDisassembler *Decoder) { in DecodeSyncI() argument
1582 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeSyncI()
1592 const MCDisassembler *Decoder) { in DecodeSyncI_MM() argument
1596 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeSyncI_MM()
1605 const MCDisassembler *Decoder) { in DecodeSynciR6() argument
1609 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeSynciR6()
1619 const MCDisassembler *Decoder) { in DecodeMSA128Mem() argument
1624 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); in DecodeMSA128Mem()
1625 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMSA128Mem()
1666 const MCDisassembler *Decoder) { in DecodeMemMMImm4() argument
1675 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) in DecodeMemMMImm4()
1685 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder) in DecodeMemMMImm4()
1691 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) in DecodeMemMMImm4()
1723 const MCDisassembler *Decoder) { in DecodeMemMMSPImm5Lsl2() argument
1727 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMSPImm5Lsl2()
1738 const MCDisassembler *Decoder) { in DecodeMemMMGPImm7Lsl2() argument
1742 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMGPImm7Lsl2()
1753 const MCDisassembler *Decoder) { in DecodeMemMMReglistImm4Lsl2() argument
1765 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) in DecodeMemMMReglistImm4Lsl2()
1777 const MCDisassembler *Decoder) { in DecodeMemMMImm9() argument
1782 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMImm9()
1783 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemMMImm9()
1797 const MCDisassembler *Decoder) { in DecodeMemMMImm12() argument
1802 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMImm12()
1803 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemMMImm12()
1808 if (DecodeRegListOperand(Inst, Insn, Address, Decoder) in DecodeMemMMImm12()
1831 const MCDisassembler *Decoder) { in DecodeMemMMImm16() argument
1836 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMemMMImm16()
1837 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMemMMImm16()
1847 const MCDisassembler *Decoder) { in DecodeFMem() argument
1852 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); in DecodeFMem()
1853 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMem()
1864 const MCDisassembler *Decoder) { in DecodeFMemMMR2() argument
1871 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg); in DecodeFMemMMR2()
1872 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMemMMR2()
1882 const MCDisassembler *Decoder) { in DecodeFMem2() argument
1887 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); in DecodeFMem2()
1888 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMem2()
1898 const MCDisassembler *Decoder) { in DecodeFMem3() argument
1903 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); in DecodeFMem3()
1904 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMem3()
1915 const MCDisassembler *Decoder) { in DecodeFMemCop2R6() argument
1920 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); in DecodeFMemCop2R6()
1921 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMemCop2R6()
1932 const MCDisassembler *Decoder) { in DecodeFMemCop2MMR6() argument
1937 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); in DecodeFMemCop2MMR6()
1938 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeFMemCop2MMR6()
1949 const MCDisassembler *Decoder) { in DecodeSpecial3LlSc() argument
1954 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt); in DecodeSpecial3LlSc()
1955 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeSpecial3LlSc()
1970 const MCDisassembler *Decoder) { in DecodeHWRegsRegisterClass() argument
1980 const MCDisassembler *Decoder) { in DecodeAFGR64RegisterClass() argument
1984 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2); in DecodeAFGR64RegisterClass()
1991 const MCDisassembler *Decoder) { in DecodeACC64DSPRegisterClass() argument
1995 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo); in DecodeACC64DSPRegisterClass()
2002 const MCDisassembler *Decoder) { in DecodeHI32DSPRegisterClass() argument
2006 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo); in DecodeHI32DSPRegisterClass()
2013 const MCDisassembler *Decoder) { in DecodeLO32DSPRegisterClass() argument
2017 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo); in DecodeLO32DSPRegisterClass()
2024 const MCDisassembler *Decoder) { in DecodeMSA128BRegisterClass() argument
2028 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo); in DecodeMSA128BRegisterClass()
2035 const MCDisassembler *Decoder) { in DecodeMSA128HRegisterClass() argument
2039 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo); in DecodeMSA128HRegisterClass()
2046 const MCDisassembler *Decoder) { in DecodeMSA128WRegisterClass() argument
2050 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo); in DecodeMSA128WRegisterClass()
2057 const MCDisassembler *Decoder) { in DecodeMSA128DRegisterClass() argument
2061 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo); in DecodeMSA128DRegisterClass()
2068 const MCDisassembler *Decoder) { in DecodeMSACtrlRegisterClass() argument
2072 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo); in DecodeMSACtrlRegisterClass()
2079 const MCDisassembler *Decoder) { in DecodeCOP0RegisterClass() argument
2083 unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo); in DecodeCOP0RegisterClass()
2090 const MCDisassembler *Decoder) { in DecodeCOP2RegisterClass() argument
2094 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo); in DecodeCOP2RegisterClass()
2101 const MCDisassembler *Decoder) { in DecodeBranchTarget() argument
2109 const MCDisassembler *Decoder) { in DecodeBranchTarget1SImm16() argument
2117 const MCDisassembler *Decoder) { in DecodeJumpTarget() argument
2125 const MCDisassembler *Decoder) { in DecodeBranchTarget21() argument
2134 const MCDisassembler *Decoder) { in DecodeBranchTarget21MM() argument
2143 const MCDisassembler *Decoder) { in DecodeBranchTarget26() argument
2152 const MCDisassembler *Decoder) { in DecodeBranchTarget7MM() argument
2160 const MCDisassembler *Decoder) { in DecodeBranchTarget10MM() argument
2168 const MCDisassembler *Decoder) { in DecodeBranchTargetMM() argument
2176 const MCDisassembler *Decoder) { in DecodeBranchTarget26MM() argument
2185 const MCDisassembler *Decoder) { in DecodeJumpTargetMM() argument
2193 const MCDisassembler *Decoder) { in DecodeJumpTargetXMM() argument
2201 const MCDisassembler *Decoder) { in DecodeAddiur2Simm7() argument
2213 const MCDisassembler *Decoder) { in DecodeLi16Imm() argument
2223 const MCDisassembler *Decoder) { in DecodePOOL16BEncodedField() argument
2231 const MCDisassembler *Decoder) { in DecodeUImmWithOffsetAndScale() argument
2241 const MCDisassembler *Decoder) { in DecodeSImmWithOffsetAndScale() argument
2248 const MCDisassembler *Decoder) { in DecodeInsSize() argument
2260 const MCDisassembler *Decoder) { in DecodeSimm19Lsl2() argument
2267 const MCDisassembler *Decoder) { in DecodeSimm18Lsl3() argument
2273 const MCDisassembler *Decoder) { in DecodeSimm9SP() argument
2288 const MCDisassembler *Decoder) { in DecodeANDI16Imm() argument
2299 const MCDisassembler *Decoder) { in DecodeRegListOperand() argument
2327 const MCDisassembler *Decoder) { in DecodeRegListOperand16() argument
2351 const MCDisassembler *Decoder) { in DecodeMovePOperands() argument
2353 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == in DecodeMovePOperands()
2358 if (static_cast<const MipsDisassembler*>(Decoder)->hasMips32r6()) in DecodeMovePOperands()
2363 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == in DecodeMovePOperands()
2368 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == in DecodeMovePOperands()
2377 const MCDisassembler *Decoder) { in DecodeMovePRegPair() argument
2420 const MCDisassembler *Decoder) { in DecodeSimm23Lsl2() argument
2428 const MCDisassembler *Decoder) { in DecodeBgtzGroupBranchMMR6() argument
2463 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); in DecodeBgtzGroupBranchMMR6()
2467 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); in DecodeBgtzGroupBranchMMR6()
2477 const MCDisassembler *Decoder) { in DecodeBlezGroupBranchMMR6() argument
2508 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); in DecodeBlezGroupBranchMMR6()
2510 MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); in DecodeBlezGroupBranchMMR6()