1257                                              ? getMemBase()->getGPR64Reg()  in addMemOperands()
1258                                              : getMemBase()->getGPR32Reg()));  in addMemOperands()
1267     Inst.addOperand(MCOperand::createReg(getMemBase()->getGPRMM16Reg()));  in addMicroMipsMemOperands()
1342     if (!getMemBase()->isGPRAsmReg())  in isMemWithSimmOffset()
1356     if (!getMemBase()->isGPRAsmReg())  in isMemWithPtrSizeOffset()
1368     return isMem() && getMemBase()->isMM16AsmReg();  in isMemWithGRPMM16Base()
1373       && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP);  in isMemWithUimmOffsetSP()
1378       && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx()  in isMemWithUimmWordAlignedOffsetSP()
1379       && (getMemBase()->getGPR32Reg() == Mips::SP);  in isMemWithUimmWordAlignedOffsetSP()
1384       && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx()  in isMemWithSimmWordAlignedOffsetGP()
1385       && (getMemBase()->getGPR32Reg() == Mips::GP);  in isMemWithSimmWordAlignedOffsetGP()
1472   MipsOperand *getMemBase() const {  in getMemBase()  function in __anon03c4d4620211::MipsOperand