907   unsigned getGPR32Reg() const {  in getGPR32Reg()  function in __anon03c4d4620211::MipsOperand
1067     Inst.addOperand(MCOperand::createReg(getGPR32Reg()));  in addGPR32ZeroAsmRegOperands()
1072     Inst.addOperand(MCOperand::createReg(getGPR32Reg()));  in addGPR32NonZeroAsmRegOperands()
1077     Inst.addOperand(MCOperand::createReg(getGPR32Reg()));  in addGPR32AsmRegOperands()
1258                                              : getMemBase()->getGPR32Reg()));  in addMemOperands()
1373       && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP);  in isMemWithUimmOffsetSP()
1379       && (getMemBase()->getGPR32Reg() == Mips::SP);  in isMemWithUimmWordAlignedOffsetSP()
1385       && (getMemBase()->getGPR32Reg() == Mips::GP);  in isMemWithSimmWordAlignedOffsetGP()
1454       return getGPR32Reg(); // FIXME: GPR64 too  in getReg()
6141   int NextReg = nextReg(((MipsOperand &)*Operands[1]).getGPR32Reg());  in ConvertXWPOperands()
6417       RegNo = isGP64bit() ? Operand.getGPR64Reg() : Operand.getGPR32Reg();  in tryParseRegister()
6804     RegNo = isGP64bit() ? Reg.getGPR64Reg() : Reg.getGPR32Reg();  in parseRegisterList()
7657   getTargetStreamer().emitDirectiveCpAdd(RegOpnd.getGPR32Reg());  in parseDirectiveCpAdd()
7689   getTargetStreamer().emitDirectiveCpLoad(RegOpnd.getGPR32Reg());  in parseDirectiveCpLoad()
7719   unsigned NewReg = RegOpnd.getGPR32Reg();  in parseDirectiveCpLocal()
7791   FuncReg = FuncRegOpnd.getGPR32Reg();  in parseDirectiveCPSetup()
7817     Save = SaveOpnd.getGPR32Reg();  in parseDirectiveCPSetup()
8683     unsigned StackReg = StackRegOpnd.getGPR32Reg();  in ParseDirective()
8735                                   ReturnRegOpnd.getGPR32Reg());  in ParseDirective()