3400     TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);  in expandLoadSingleImmToFPR()
3520       TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3530       TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3533       TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3534       TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);  in expandLoadDoubleImmToFPR()
4241       TOut.emitRR(DivOp, RsReg, ATReg, IDLoc, STI);  in expandDivRem()
4264     TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);  in expandDivRem()
4282   TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);  in expandDivRem()
4350     TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);  in expandTrunc()
4351     TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);  in expandTrunc()
4355     TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI);  in expandTrunc()
4357     TOut.emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32)  in expandTrunc()
4360     TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI);  in expandTrunc()
4365   TOut.emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32)  in expandTrunc()
5169   TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT,  in expandMulImm()
5189   TOut.emitRR(Inst.getOpcode() == Mips::MULOMacro ? Mips::MULT : Mips::DMULT,  in expandMulO()
5231   TOut.emitRR(Inst.getOpcode() == Mips::MULOUMacro ? Mips::MULTu : Mips::DMULTu,  in expandMulOU()
5262   TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI);  in expandDMULMacro()
5743       TOut.emitRR(Opcode, RtReg, BaseReg, IDLoc, STI);  in expandSaaAddr()
5755   TOut.emitRR(Opcode, RtReg, ATReg, IDLoc, STI);  in expandSaaAddr()