2866   const MCOperand &DstRegOp = Inst.getOperand(0);  in expandLoadImm()  local
2867   assert(DstRegOp.isReg() && "expected register operand kind");  in expandLoadImm()
2869   if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,  in expandLoadImm()
3614   const MCOperand &DstRegOp = Inst.getOperand(0);  in expandBranchImm()  local
3615   assert(DstRegOp.isReg() && "expected register operand kind");  in expandBranchImm()
3650       TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO,  in expandBranchImm()
3654       TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,  in expandBranchImm()
3668       TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg,  in expandBranchImm()
3672       TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI);  in expandBranchImm()
3683   const MCOperand &DstRegOp = Inst.getOperand(StartOp);  in expandMem16Inst()  local
3684   assert(DstRegOp.isReg() && "expected register operand kind");  in expandMem16Inst()
3691   unsigned DstReg = DstRegOp.getReg();  in expandMem16Inst()
3810   const MCOperand &DstRegOp = Inst.getOperand(StartOp);  in expandMem9Inst()  local
3811   assert(DstRegOp.isReg() && "expected register operand kind");  in expandMem9Inst()
3818   unsigned DstReg = DstRegOp.getReg();  in expandMem9Inst()
4378   const MCOperand &DstRegOp = Inst.getOperand(0);  in expandUlh()  local
4379   assert(DstRegOp.isReg() && "expected register operand kind");  in expandUlh()
4386   unsigned DstReg = DstRegOp.getReg();  in expandUlh()
4430   const MCOperand &DstRegOp = Inst.getOperand(0);  in expandUsh()  local
4431   assert(DstRegOp.isReg() && "expected register operand kind");  in expandUsh()
4438   unsigned DstReg = DstRegOp.getReg();  in expandUsh()
4481   const MCOperand &DstRegOp = Inst.getOperand(0);  in expandUxw()  local
4482   assert(DstRegOp.isReg() && "expected register operand kind");  in expandUxw()
4489   unsigned DstReg = DstRegOp.getReg();  in expandUxw()