Lines Matching refs:Ins
446 const SmallVectorImpl<ISD::InputArg> &Ins) { in AnalyzeVarArgs() argument
447 State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack); in AnalyzeVarArgs()
550 const SmallVectorImpl<ISD::InputArg> &Ins) { in AnalyzeRetResult() argument
551 State.AnalyzeCallResult(Ins, RetCC_MSP430); in AnalyzeRetResult()
568 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerFormalArguments() argument
576 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); in LowerFormalArguments()
578 if (Ins.empty()) in LowerFormalArguments()
591 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall() local
608 Outs, OutVals, Ins, dl, DAG, InVals); in LowerCall()
619 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCCCArguments() argument
630 AnalyzeArguments(CCInfo, ArgLocs, Ins); in LowerCCCArguments()
677 ISD::ArgFlagsTy Flags = Ins[i].Flags; in LowerCCCArguments()
708 if (Ins[i].Flags.isSRet()) { in LowerCCCArguments()
809 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCCCCallTo() argument
928 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, in LowerCCCCallTo()
937 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCallResult() argument
945 AnalyzeReturnValues(CCInfo, RVLocs, Ins); in LowerCallResult()