71       HexagonMCInstrInfo::isPredReg(RI, R)) {  in initReg()
82     for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());  in initReg()
84       if (!MCSubRegIterator(*SRI, &RI).isValid())  in initReg()
129       else if (HexagonMCInstrInfo::isPredReg(RI, R) &&  in init()
151     for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid());  in init()
153       if (MCSubRegIterator(*SRI, &RI).isValid())  in init()
173                HexagonMCInstrInfo::isPredReg(RI, *SRI))  in init()
199         if (HexagonMCInstrInfo::isPredReg(RI, P))  in init()
207     : Context(Context), MCB(mcb), RI(ri), MCII(MCII), STI(STI),  in HexagonMCChecker()
215     : Context(Other.Context), MCB(Other.MCB), RI(Other.RI), MCII(Other.MCII),  in HexagonMCChecker()
544                                        Twine(RI.getName(Register)) + "'");  in checkRegistersReadOnly()
575       for (auto K = MCRegAliasIterator(I.getOperand(J).getReg(), &RI, true);  in registerProducer()
601       for (MCRegAliasIterator Alias(RegDef, &RI, true); Alias.isValid();  in checkRegisterCurDefs()
606         reportWarning("Register `" + Twine(RI.getName(RegDef)) +  in checkRegisterCurDefs()
631       unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;  in checkRegisters()
635     if (!HexagonMCInstrInfo::isPredReg(RI, R) && Defs[R].size() > 1) {  in checkRegisters()
644         unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;  in checkRegisters()
688         reportWarning("register `" + Twine(RI.getName(R)) +  in checkRegisters()
776   reportError("register `" + Twine(RI.getName(Register)) +  in reportErrorRegisters()
781   reportError("register `" + Twine(RI.getName(Register)) +  in reportErrorNewValue()
814       reportError("register pair `" + Twine(RI.getName(R)) +  in checkLegalVecRegPair()
832       reportError("register `" + Twine(RI.getName(R)) + ".tmp" +  in checkHVXAccum()