289       MachineInstr &MI2 = *SI.getSUnit()->getInstr();  in apply()
296         for (SDep &PI : SI.getSUnit()->Preds) {  in apply()
297           if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)  in apply()
300           SI.getSUnit()->setDepthDirty();  in apply()
485       MachineInstr *DDst = DDep.getSUnit()->getInstr();  in adjustSchedDependency()
573     if (!I.isAssignedRegDep() || I.getSUnit() != Dst)  in restoreLatency()
621     if (!I.isAssignedRegDep() || I.getSUnit() != Dst)  in changeLatency()
638         !I.getSUnit()->getInstr()->isPseudo())  in getZeroLatency()
639       return I.getSUnit();  in getZeroLatency()
716       if (ExclSrc.count(I.getSUnit()) == 0 &&  in isBestZeroLatency()
717           isBestZeroLatency(I.getSUnit(), DstBest, TII, ExclSrc, ExclDst))  in isBestZeroLatency()
718         changeLatency(I.getSUnit(), DstBest, 0);  in isBestZeroLatency()
724       if (ExclDst.count(I.getSUnit()) == 0 &&  in isBestZeroLatency()
725           isBestZeroLatency(SrcBest, I.getSUnit(), TII, ExclSrc, ExclDst))  in isBestZeroLatency()
726         changeLatency(SrcBest, I.getSUnit(), 0);  in isBestZeroLatency()