648              .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
651               .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
657              .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
661               .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())  in splitMemRef()
767     .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());  in splitExt()
807       .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
832         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
835         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
838         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
844         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)  in splitShift()
855         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)  in splitShift()
866       .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));  in splitShift()
878         .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);  in splitShift()
881         .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);  in splitShift()
884         .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))  in splitShift()
942       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
943       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);  in splitAslOr()
949       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)  in splitAslOr()
950       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)  in splitAslOr()
954       .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)  in splitAslOr()
971       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()
982       .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);  in splitAslOr()