Lines Matching refs:HRI
134 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) { in isDblRegForSubInst() argument
135 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && in isDblRegForSubInst()
136 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); in isDblRegForSubInst()
858 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in copyPhysReg() local
919 LivePhysRegs LiveAtMI(HRI); in copyPhysReg()
921 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg()
922 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg()
950 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n'; in copyPhysReg()
1048 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in expandPostRAPseudo() local
1049 LivePhysRegs LiveIn(HRI), LiveOut(HRI); in expandPostRAPseudo()
1126 .addReg(HRI.getFrameRegister()) in expandPostRAPseudo()
1133 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1134 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1148 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1157 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1168 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1183 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1184 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1188 HRI.getSubReg(DstReg, Hexagon::vsub_lo)) in expandPostRAPseudo()
1193 HRI.getSubReg(DstReg, Hexagon::vsub_hi)) in expandPostRAPseudo()
1206 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1222 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1223 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1229 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo)) in expandPostRAPseudo()
1234 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi)) in expandPostRAPseudo()
1282 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1283 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1284 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1285 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1287 HRI.getSubReg(DstReg, Hexagon::isub_hi)) in expandPostRAPseudo()
1291 HRI.getSubReg(DstReg, Hexagon::isub_lo)) in expandPostRAPseudo()
1307 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1308 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1309 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1310 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1311 Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1312 Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1314 HRI.getSubReg(DstReg, Hexagon::isub_hi)) in expandPostRAPseudo()
1319 HRI.getSubReg(DstReg, Hexagon::isub_lo)) in expandPostRAPseudo()
1403 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo()
1404 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo()
1415 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo()
1416 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo()
1724 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in ClobbersPredicate() local
1730 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg()); in ClobbersPredicate()
1738 if (!MI.modifiesRegister(PR, &HRI)) in ClobbersPredicate()
2199 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in isDependent() local
2216 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent()
2221 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent()
3887 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in getDuplexCandidateGroup() local
3905 HRI.getStackRegister() == SrcReg && in getDuplexCandidateGroup()
3962 if (isDblRegForSubInst(DstReg, HRI) && in getDuplexCandidateGroup()
3964 HRI.getStackRegister() == SrcReg && in getDuplexCandidateGroup()
4028 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() && in getDuplexCandidateGroup()
4070 if (isDblRegForSubInst(Src2Reg, HRI) && in getDuplexCandidateGroup()
4072 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() && in getDuplexCandidateGroup()
4125 HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() && in getDuplexCandidateGroup()
4215 if (isDblRegForSubInst(DstReg, HRI) && in getDuplexCandidateGroup()
4230 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
4240 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
4293 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in getOperandLatency() local
4300 for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) { in getOperandLatency()
4301 int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI); in getOperandLatency()
4311 for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) { in getOperandLatency()
4312 int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI); in getOperandLatency()
4464 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); in getMemAccessSize() local
4467 return HRI.getSpillSize(Hexagon::HvxVRRegClass); in getMemAccessSize()