153 bool HexagonInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {  in isAsCheapAsAMove()  argument
184 bool HexagonInstrInfo::shouldSink(const MachineInstr &MI) const {  in shouldSink()  argument
198       SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {  in findLoopInstr()
288                                                int &FrameIndex) const {  in isLoadFromStackSlot()
336                                               int &FrameIndex) const {  in isStoreToStackSlot()
387     SmallVectorImpl<const MachineMemOperand *> &Accesses) const {  in hasLoadFromStackSlot()
405     SmallVectorImpl<const MachineMemOperand *> &Accesses) const {  in hasStoreToStackSlot()
437                                      bool AllowModify) const {  in analyzeBranch()
604                                         int *BytesRemoved) const {  in removeBranch()
631                                         int *BytesAdded) const {  in insertBranch()
748   bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {  in shouldIgnoreForPipelining()  argument
803 HexagonInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {  in analyzeLoopForPipelining()
819       BranchProbability Probability) const {  in isProfitableToIfCvt()
825       unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)  in isProfitableToIfCvt()
831       unsigned NumInstrs, BranchProbability Probability) const {  in isProfitableToDupForIfCvt()
857                                    MCRegister SrcReg, bool KillSrc) const {  in copyPhysReg()
957       const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {  in storeRegToStackSlot()  argument
1003     const TargetRegisterInfo *TRI) const {  in loadRegFromStackSlot()  argument
1044 bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {  in expandPostRAPseudo()
1436         bool isConstant(const MachineFrameInfo *) const override {  in expandPostRAPseudo()  argument
1439         bool isAliased(const MachineFrameInfo *) const override {  in expandPostRAPseudo()  argument
1442         bool mayAlias(const MachineFrameInfo *) const override {  in expandPostRAPseudo()  argument
1445         void printCustom(raw_ostream &OS) const override {  in expandPostRAPseudo()
1538 HexagonInstrInfo::expandVGatherPseudo(MachineInstr &MI) const {  in expandVGatherPseudo()
1627       SmallVectorImpl<MachineOperand> &Cond) const {  in reverseBranchCondition()
1642       MachineBasicBlock::iterator MI) const {  in insertNoop()
1647 bool HexagonInstrInfo::isPostIncrement(const MachineInstr &MI) const {  in isPostIncrement()  argument
1659 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {  in isPredicated()  argument
1665     MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {  in PredicateInstruction()
1716       ArrayRef<MachineOperand> Pred2) const {  in SubsumesPredicate()
1723                                          bool SkipDead) const {  in ClobbersPredicate()
1748 bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {  in isPredicable()  argument
1786                                             const MachineFunction &MF) const {  in isSchedulingBoundary()  argument
1834                                               const TargetSubtargetInfo *STI) const {  in getInlineAsmLength()  argument
1861       const InstrItineraryData *II, const ScheduleDAG *DAG) const {  in CreateTargetPostRAHazardRecognizer()  argument
1873                                       int64_t &Value) const {  in analyzeCompare()
1963                                            unsigned *PredCost) const {  in getInstrLatency()
1968     const TargetSubtargetInfo &STI) const {  in CreateTargetScheduleState()  argument
1978     const MachineInstr &MIa, const MachineInstr &MIb) const {  in areMemAccessesTriviallyDisjoint()  argument
2036       int &Value) const {  in getIncrementValue()
2058 HexagonInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {  in decomposeMachineOperandsTargetFlags()
2092 unsigned HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {  in createVR()
2109 bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr &MI) const {  in isAbsoluteSet()  argument
2113 bool HexagonInstrInfo::isAccumulator(const MachineInstr &MI) const {  in isAccumulator()  argument
2118 bool HexagonInstrInfo::isBaseImmOffset(const MachineInstr &MI) const {  in isBaseImmOffset()  argument
2122 bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {  in isComplex()  argument
2131 bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const {  in isCompoundBranchInstr()  argument
2137 bool HexagonInstrInfo::isConstExtended(const MachineInstr &MI) const {  in isConstExtended()  argument
2180 bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const {  in isDeallocRet()  argument
2196       const MachineInstr &ConsMI) const {  in isDependent()  argument
2230 bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {  in isDotCurInst()  argument
2241 bool HexagonInstrInfo::isDotNewInst(const MachineInstr &MI) const {  in isDotNewInst()  argument
2250       const MachineInstr &MIb) const {  in isDuplexPair()  argument
2256 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {  in isEndLoopN()
2261 bool HexagonInstrInfo::isExpr(unsigned OpType) const {  in isExpr()
2275 bool HexagonInstrInfo::isExtendable(const MachineInstr &MI) const {  in isExtendable()  argument
2297 bool HexagonInstrInfo::isExtended(const MachineInstr &MI) const {  in isExtended()  argument
2310 bool HexagonInstrInfo::isFloat(const MachineInstr &MI) const {  in isFloat()  argument
2318       const MachineInstr &J) const {  in isHVXMemWithAIndirect()  argument
2326 bool HexagonInstrInfo::isIndirectCall(const MachineInstr &MI) const {  in isIndirectCall()  argument
2337 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr &MI) const {  in isIndirectL4Return()  argument
2351 bool HexagonInstrInfo::isJumpR(const MachineInstr &MI) const {  in isJumpR()  argument
2370       unsigned offset) const {  in isJumpWithinBranchRange()
2411 bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr &MI) const {  in isLateSourceInstr()  argument
2417 bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {  in isLoopN()  argument
2429 bool HexagonInstrInfo::isMemOp(const MachineInstr &MI) const {  in isMemOp()  argument
2461 bool HexagonInstrInfo::isNewValue(const MachineInstr &MI) const {  in isNewValue()  argument
2466 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {  in isNewValue()
2471 bool HexagonInstrInfo::isNewValueInst(const MachineInstr &MI) const {  in isNewValueInst()  argument
2475 bool HexagonInstrInfo::isNewValueJump(const MachineInstr &MI) const {  in isNewValueJump()  argument
2479 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {  in isNewValueJump()
2483 bool HexagonInstrInfo::isNewValueStore(const MachineInstr &MI) const {  in isNewValueStore()  argument
2488 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {  in isNewValueStore()
2495     unsigned OperandNum) const {  in isOperandExtended()
2501 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {  in isPredicatedNew()  argument
2507 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {  in isPredicatedNew()
2513 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {  in isPredicatedTrue()  argument
2519 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {  in isPredicatedTrue()
2527 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {  in isPredicated()
2532 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {  in isPredicateLate()
2537 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {  in isPredictedTaken()
2544 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr &MI) const {  in isSaveCalleeSavedRegsCall()  argument
2551 bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr &MI) const {  in isSignExtendingLoad()  argument
2629 bool HexagonInstrInfo::isSolo(const MachineInstr &MI) const {  in isSolo()  argument
2634 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr &MI) const {  in isSpillPredRegOp()  argument
2644 bool HexagonInstrInfo::isTailCall(const MachineInstr &MI) const {  in isTailCall()  argument
2655 bool HexagonInstrInfo::isTC1(const MachineInstr &MI) const {  in isTC1()  argument
2660 bool HexagonInstrInfo::isTC2(const MachineInstr &MI) const {  in isTC2()  argument
2665 bool HexagonInstrInfo::isTC2Early(const MachineInstr &MI) const {  in isTC2Early()  argument
2670 bool HexagonInstrInfo::isTC4x(const MachineInstr &MI) const {  in isTC4x()  argument
2677       const MachineInstr &MI2) const {  in isToBeScheduledASAP()  argument
2694 bool HexagonInstrInfo::isHVXVec(const MachineInstr &MI) const {  in isHVXVec()  argument
2700 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, int Offset) const {  in isValidAutoIncImm()
2738       const TargetRegisterInfo *TRI, bool Extend) const {  in isValidOffset()
2919 bool HexagonInstrInfo::isVecAcc(const MachineInstr &MI) const {  in isVecAcc()  argument
2923 bool HexagonInstrInfo::isVecALU(const MachineInstr &MI) const {  in isVecALU()  argument
2932       const MachineInstr &ConsMI) const {  in isVecUsableNextPacket()  argument
2945 bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr &MI) const {  in isZeroExtendingLoad()  argument
3025       const MachineInstr &MI2) const {  in addLatencyToSchedule()  argument
3036     const TargetRegisterInfo *TRI) const {  in getMemOperandsWithOffsetWidth()  argument
3047       const MachineInstr &Second) const {  in canExecuteInBundle()  argument
3071 bool HexagonInstrInfo::doesNotReturn(const MachineInstr &CallMI) const {  in doesNotReturn()  argument
3076 bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {  in hasEHLabel()  argument
3085 bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr &MI) const {  in hasNonExtEquivalent()  argument
3120 bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr &MI) const {  in hasPseudoInstrPair()  argument
3125 bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)  in hasUncondBranch()
3137 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const {  in mayBeCurLoad()  argument
3144 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr &MI) const {  in mayBeNewStore()  argument
3153       const MachineInstr &ConsMI) const {  in producesStall()  argument
3171       MachineBasicBlock::const_instr_iterator BII) const {  in producesStall()
3191       unsigned PredReg) const {  in predCanBeUsedAsDotNew()
3225 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {  in PredOpcodeHasJMP_c()
3236 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {  in predOpcodeHasNot()
3242 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {  in getAddrMode()  argument
3253                                                    unsigned &AccessSize) const {  in getBaseAndOffset()
3285       unsigned &BasePos, unsigned &OffsetPos) const {  in getBaseAndOffsetPosition()
3322       MachineBasicBlock& MBB) const {  in getBranchingInstrs()
3379 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const {  in getCExtOpNum()  argument
3387       const MachineInstr &MI) const {  in getCompoundCandidateGroup()  argument
3475       const MachineInstr &GB) const {  in getCompoundOpcode()  argument
3502                                       bool ForBigCore) const {  in getDuplexOpcode()
3558 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {  in getCondOpcode()
3570 int HexagonInstrInfo::getDotCurOp(const MachineInstr &MI) const {  in getDotCurOp()  argument
3590 int HexagonInstrInfo::getNonDotCurOp(const MachineInstr &MI) const {  in getNonDotCurOp()  argument
3691 int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {  in getDotNewOp()  argument
3733       const MachineBranchProbabilityInfo *MBPI) const {  in getDotNewPredJumpOp()  argument
3819       const MachineBranchProbabilityInfo *MBPI) const {  in getDotNewPredOp()  argument
3833 int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {  in getDotOldOp()  argument
3885       const MachineInstr &MI) const {  in getDuplexCandidateGroup()  argument
4264 short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr &MI) const {  in getEquivalentHWInstr()  argument
4269       const InstrItineraryData *ItinData, const MachineInstr &MI) const {  in getInstrTimingClassLatency()  argument
4292                                         unsigned UseIdx) const {  in getOperandLatency()
4335       SmallVectorImpl<MachineOperand> &Cond) const {  in getInvertedPredSense()
4343 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {  in getInvertedPredicatedOpcode()  argument
4354 int HexagonInstrInfo::getMaxValue(const MachineInstr &MI) const {  in getMaxValue()  argument
4368 bool HexagonInstrInfo::isAddrModeWithOffset(const MachineInstr &MI) const {  in isAddrModeWithOffset()  argument
4396 bool HexagonInstrInfo::isPureSlot0(const MachineInstr &MI) const {  in isPureSlot0()  argument
4408 bool HexagonInstrInfo::isRestrictNoSlot1Store(const MachineInstr &MI) const {  in isRestrictNoSlot1Store()  argument
4415                                           bool ToBigInstrs) const {  in changeDuplexOpcode()
4433                                              bool ToBigInstrs) const {  in translateInstrsForDup()
4443     MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const {  in translateInstrsForDup()
4451 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {  in getMemAccessSize()  argument
4474 int HexagonInstrInfo::getMinValue(const MachineInstr &MI) const {  in getMinValue()  argument
4488 short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const {  in getNonExtOpcode()  argument
4513       unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {  in getPredReg()
4532 short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr &MI) const {  in getPseudoInstrPair()  argument
4536 short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {  in getRegForm()  argument
4544 unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {  in getSize()  argument
4578 uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const {  in getType()  argument
4583 InstrStage::FuncUnits HexagonInstrInfo::getUnits(const MachineInstr &MI) const {  in getUnits()  argument
4591 unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {  in nonDbgBBSize()  argument
4596       MachineBasicBlock::const_iterator BundleHead) const {  in nonDbgBundleSize()
4605 void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {  in immediateExtend()
4619       MachineInstr &MI, MachineBasicBlock *NewTarget) const {  in invertAndChangeJumpTarget()
4639 void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {  in genAllInsnTimingClasses()
4661 bool HexagonInstrInfo::reversePredSense(MachineInstr &MI) const {  in reversePredSense()
4668 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {  in reversePrediction()
4679 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)  in validateBranchCond()
4685 setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const {  in setBundleNoShuf()
4694 bool HexagonInstrInfo::getBundleNoShuf(const MachineInstr &MIB) const {  in getBundleNoShuf()  argument
4701 short HexagonInstrInfo::changeAddrMode_abs_io(short Opc) const {  in changeAddrMode_abs_io()
4705 short HexagonInstrInfo::changeAddrMode_io_abs(short Opc) const {  in changeAddrMode_io_abs()
4709 short HexagonInstrInfo::changeAddrMode_io_pi(short Opc) const {  in changeAddrMode_io_pi()
4713 short HexagonInstrInfo::changeAddrMode_io_rr(short Opc) const {  in changeAddrMode_io_rr()
4717 short HexagonInstrInfo::changeAddrMode_pi_io(short Opc) const {  in changeAddrMode_pi_io()
4721 short HexagonInstrInfo::changeAddrMode_rr_io(short Opc) const {  in changeAddrMode_rr_io()
4725 short HexagonInstrInfo::changeAddrMode_rr_ur(short Opc) const {  in changeAddrMode_rr_ur()
4729 short HexagonInstrInfo::changeAddrMode_ur_rr(short Opc) const {  in changeAddrMode_ur_rr()