180           Sub(Op.getSubReg()) {}  in RegisterRef()
181       RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}  in RegisterRef()
184         return Reg == RR.Reg && Sub == RR.Sub;  in operator ==()
188         return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);  in operator <()
192       unsigned Sub;  member
199     unsigned getMaskForSub(unsigned Sub);
201     LaneBitmask getLaneMask(Register Reg, unsigned Sub);
261 unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) {  in INITIALIZE_PASS_DEPENDENCY()
262   switch (Sub) {  in INITIALIZE_PASS_DEPENDENCY()
289 LaneBitmask HexagonExpandCondsets::getLaneMask(Register Reg, unsigned Sub) {  in getLaneMask()  argument
291   return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)  in getLaneMask()
297   unsigned Mask = getMaskForSub(RR.Sub) | Exec;  in addRefToMap()
310   unsigned Mask = getMaskForSub(RR.Sub) | Exec;  in isRefInMap()
522       MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub);  in updateDeadsInRange()
594     MCRegister PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);  in getCondTfrOpcode()
701       MachineInstrBuilder(MF, MI).addReg(RT.Reg, S, RT.Sub);  in split()
779       if (RR.Sub == RD.Sub)  in getReachingDefForPred()
781       if (RR.Sub == 0 || RD.Sub == 0)  in getReachingDefForPred()
926       Op.setSubReg(RN.Sub);  in renameInRange()
1009         assert(RR.Sub && "Expecting a subregister on <def,read-undef>");  in predicate()
1013         RR.Sub = 0;  in predicate()
1102     BW = (RR.Sub != 0) ? 32 : 64;  in isIntReg()
1144                     << printReg(R1.Reg, TRI, R1.Sub) << "  " << L1 << "\n  "  in coalesceRegisters()
1145                     << printReg(R2.Reg, TRI, R2.Sub) << "  " << L2 << "\n");  in coalesceRegisters()
1146   if (R1.Sub || R2.Sub)  in coalesceRegisters()