203           const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
779       unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) {  in buildMux()  argument
805     .addReg(TR, 0, TSR)  in buildMux()
818     unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0;  in updatePhiNodes()  local
824         TR = RO.getReg(), TSR = RO.getSubReg();  in updatePhiNodes()
832     if (TR == 0)  in updatePhiNodes()
833       TR = SR, TSR = SSR;  in updatePhiNodes()
837     assert(TR || FR);  in updatePhiNodes()
840     if (TR && FR) {  in updatePhiNodes()
844                       FP.PredR, TR, TSR, FR, FSR);  in updatePhiNodes()
845     } else if (TR) {  in updatePhiNodes()
846       MuxR = TR;  in updatePhiNodes()