204           unsigned TSR, unsigned FR, unsigned FSR);
779       unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) {  in buildMux()  argument
806     .addReg(FR, 0, FSR);  in buildMux()
818     unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0;  in updatePhiNodes()  local
826         FR = RO.getReg(), FSR = RO.getSubReg();  in updatePhiNodes()
834     else if (FR == 0)  in updatePhiNodes()
835       FR = SR, FSR = SSR;  in updatePhiNodes()
837     assert(TR || FR);  in updatePhiNodes()
840     if (TR && FR) {  in updatePhiNodes()
844                       FP.PredR, TR, TSR, FR, FSR);  in updatePhiNodes()
849       MuxR = FR;  in updatePhiNodes()