Lines Matching refs:RegisterCell
231 static bool isEqual(const BitTracker::RegisterCell &RC1, uint16_t B1,
232 const BitTracker::RegisterCell &RC2, uint16_t B2, uint16_t W);
233 static bool isZero(const BitTracker::RegisterCell &RC, uint16_t B,
235 static bool getConst(const BitTracker::RegisterCell &RC, uint16_t B,
342 bool HexagonBitSimplify::isEqual(const BitTracker::RegisterCell &RC1, in isEqual()
343 uint16_t B1, const BitTracker::RegisterCell &RC2, uint16_t B2, in isEqual()
358 bool HexagonBitSimplify::isZero(const BitTracker::RegisterCell &RC, in isZero()
367 bool HexagonBitSimplify::getConst(const BitTracker::RegisterCell &RC, in getConst()
1308 const BitTracker::RegisterCell &DC = BT.lookup(RD.Reg); in usedBitsEqual()
1309 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in usedBitsEqual()
1350 const BitTracker::RegisterCell &DC = BT.lookup(RD.Reg); in processBlock()
1367 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in processBlock()
1511 const BitTracker::RegisterCell &DRC = BT.lookup(DR); in processBlock()
1577 const BitTracker::RegisterCell &InpRC = BT.lookup(Inp.Reg); in findMatch()
1586 const BitTracker::RegisterCell &RC = BT.lookup(R); in findMatch()
1788 bool matchHalf(unsigned SelfR, const BitTracker::RegisterCell &RC,
1792 bool matchPackhl(unsigned SelfR, const BitTracker::RegisterCell &RC,
1799 const BitTracker::RegisterCell &RC);
1801 const BitTracker::RegisterCell &RC);
1803 const BitTracker::RegisterCell &RC);
1805 const BitTracker::RegisterCell &RC);
1807 const BitTracker::RegisterCell &RC, const RegisterSet &AVs);
1809 const BitTracker::RegisterCell &RC);
1811 const BitTracker::RegisterCell &RC, const RegisterSet &AVs);
1832 const BitTracker::RegisterCell &RC, unsigned B, RegHalf &RH) { in matchHalf()
1860 const BitTracker::RegisterCell &SC = BT.lookup(Reg); in matchHalf()
1919 const BitTracker::RegisterCell &RC, BitTracker::RegisterRef &Rs, in matchPackhl()
1958 const BitTracker::RegisterCell &RC = BT.lookup(RS.Reg); in genStoreUpperHalf()
2003 const BitTracker::RegisterCell &RC = BT.lookup(RS.Reg); in genStoreImmediate()
2049 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genPackhl()
2076 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genExtractHalf()
2115 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genCombineHalf()
2147 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in genExtractLow()
2181 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in genExtractLow()
2207 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC, in genBitSplit()
2227 auto ctlz = [] (const BitTracker::RegisterCell &C) -> unsigned { in genBitSplit()
2268 const BitTracker::RegisterCell &SC = BT.lookup(S); in genBitSplit()
2360 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC) { in simplifyTstbit()
2375 const BitTracker::RegisterCell &SC = BT.lookup(RS.Reg); in simplifyTstbit()
2420 BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC, in simplifyExtractLow()
2507 const BitTracker::RegisterCell &SC = BT.lookup(R); in simplifyExtractLow()
2635 const BitTracker::RegisterCell &SC = BT.lookup(SR.Reg); in simplifyRCmp0()
2653 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0()
2721 BitTracker::RegisterCell NewRC(W); in simplifyRCmp0()
2765 const BitTracker::RegisterCell &RC = BT.lookup(RD.Reg); in processBlock()
3005 const BitTracker::RegisterCell &RC = BTP->lookup(Reg); in isConst()
3059 const BitTracker::RegisterCell &OutC = BTP->lookup(OutR); in isShuffleOf()
3074 const BitTracker::RegisterCell &OutC1 = BTP->lookup(OutR1); in isSameShuffle()
3075 const BitTracker::RegisterCell &OutC2 = BTP->lookup(OutR2); in isSameShuffle()