Lines Matching refs:DestReg

436                                          Register DestReg, int FI,  in loadRegFromStackSlot()  argument
470 BuildMI(MBB, I, DL, get(Opcode), DestReg) in loadRegFromStackSlot()
478 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
481 CSKY::CARRYRegClass.contains(DestReg)) { in copyPhysReg()
483 BuildMI(MBB, I, DL, get(CSKY::BTSTI32), DestReg) in copyPhysReg()
488 BuildMI(MBB, I, DL, get(CSKY::BTSTI16), DestReg) in copyPhysReg()
496 CSKY::GPRRegClass.contains(DestReg)) { in copyPhysReg()
499 BuildMI(MBB, I, DL, get(CSKY::MVC32), DestReg) in copyPhysReg()
502 assert(DestReg < CSKY::R16); in copyPhysReg()
503 assert(DestReg < CSKY::R8); in copyPhysReg()
504 BuildMI(MBB, I, DL, get(CSKY::MOVI16), DestReg).addImm(0); in copyPhysReg()
506 .addReg(DestReg, RegState::Define) in copyPhysReg()
508 .addReg(DestReg, getKillRegState(true)) in copyPhysReg()
509 .addReg(DestReg, getKillRegState(true)) in copyPhysReg()
513 .addReg(DestReg) in copyPhysReg()
520 if (CSKY::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
522 else if (v2sf && CSKY::sFPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
524 else if (v3sf && CSKY::FPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
526 else if (v2df && CSKY::sFPR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
528 else if (v3df && CSKY::FPR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
531 CSKY::GPRRegClass.contains(DestReg)) in copyPhysReg()
534 CSKY::GPRRegClass.contains(DestReg)) in copyPhysReg()
537 CSKY::GPRRegClass.contains(DestReg)) in copyPhysReg()
540 CSKY::GPRRegClass.contains(DestReg)) in copyPhysReg()
543 CSKY::sFPR32RegClass.contains(DestReg)) in copyPhysReg()
546 CSKY::FPR32RegClass.contains(DestReg)) in copyPhysReg()
549 CSKY::sFPR64RegClass.contains(DestReg)) in copyPhysReg()
552 CSKY::FPR64RegClass.contains(DestReg)) in copyPhysReg()
555 LLVM_DEBUG(dbgs() << "src = " << SrcReg << ", dst = " << DestReg); in copyPhysReg()
560 BuildMI(MBB, I, DL, get(Opcode), DestReg) in copyPhysReg()