Lines Matching refs:AVR
63 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs)) in emitPrologue()
71 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr)) in emitPrologue()
72 .addReg(AVR::R1R0, RegState::Kill) in emitPrologue()
75 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0) in emitPrologue()
78 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
79 .addReg(AVR::R0, RegState::Kill) in emitPrologue()
81 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) in emitPrologue()
82 .addReg(AVR::R1, RegState::Define) in emitPrologue()
83 .addReg(AVR::R1, RegState::Kill) in emitPrologue()
84 .addReg(AVR::R1, RegState::Kill) in emitPrologue()
99 (MBBI->getOpcode() == AVR::PUSHRr || MBBI->getOpcode() == AVR::PUSHWRr)) { in emitPrologue()
104 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28) in emitPrologue()
105 .addReg(AVR::SP) in emitPrologue()
110 MBBJ.addLiveIn(AVR::R29R28); in emitPrologue()
118 unsigned Opcode = (isUInt<6>(FrameSize)) ? AVR::SBIWRdK : AVR::SUBIWRdK; in emitPrologue()
120 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28) in emitPrologue()
121 .addReg(AVR::R29R28, RegState::Kill) in emitPrologue()
128 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP) in emitPrologue()
129 .addReg(AVR::R29R28) in emitPrologue()
145 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R0); in restoreStatusRegister()
146 BuildMI(MBB, MBBI, DL, TII.get(AVR::OUTARr)) in restoreStatusRegister()
148 .addReg(AVR::R0, RegState::Kill); in restoreStatusRegister()
149 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPWRd), AVR::R1R0); in restoreStatusRegister()
184 if (Opc != AVR::POPRd && Opc != AVR::POPWRd && !PI->isTerminator()) { in emitEpilogue()
196 Opcode = AVR::ADIWRdK; in emitEpilogue()
198 Opcode = AVR::SUBIWRdK; in emitEpilogue()
203 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28) in emitEpilogue()
204 .addReg(AVR::R29R28, RegState::Kill) in emitEpilogue()
211 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP) in emitEpilogue()
212 .addReg(AVR::R29R28, RegState::Kill); in emitEpilogue()
263 BuildMI(MBB, MI, DL, TII.get(AVR::PUSHRr)) in spillCalleeSavedRegisters()
292 BuildMI(MBB, MI, DL, TII.get(AVR::POPRd), Reg); in restoreCalleeSavedRegisters()
312 if (Opcode != AVR::STDSPQRr && Opcode != AVR::STDWSPQRr) in fixStackStores()
315 assert(MI.getOperand(0).getReg() == AVR::SP && in fixStackStores()
321 (Opcode == AVR::STDWSPQRr) ? AVR::STDWPtrQRr : AVR::STDPtrQRr; in fixStackStores()
324 MI.getOperand(0).setReg(AVR::R31R30); in fixStackStores()
354 BuildMI(MBB, MI, DL, TII.get(AVR::SPREAD), AVR::R31R30).addReg(AVR::SP); in eliminateCallFramePseudoInstr()
357 BuildMI(MBB, MI, DL, TII.get(AVR::SUBIWRdK), AVR::R31R30) in eliminateCallFramePseudoInstr()
358 .addReg(AVR::R31R30, RegState::Kill) in eliminateCallFramePseudoInstr()
362 BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP).addReg(AVR::R31R30); in eliminateCallFramePseudoInstr()
378 AddOpcode = AVR::ADIWRdK; in eliminateCallFramePseudoInstr()
380 AddOpcode = AVR::SUBIWRdK; in eliminateCallFramePseudoInstr()
385 BuildMI(MBB, MI, DL, TII.get(AVR::SPREAD), AVR::R31R30).addReg(AVR::SP); in eliminateCallFramePseudoInstr()
387 MachineInstr *New = BuildMI(MBB, MI, DL, TII.get(AddOpcode), AVR::R31R30) in eliminateCallFramePseudoInstr()
388 .addReg(AVR::R31R30, RegState::Kill) in eliminateCallFramePseudoInstr()
392 BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP) in eliminateCallFramePseudoInstr()
393 .addReg(AVR::R31R30, RegState::Kill); in eliminateCallFramePseudoInstr()
406 SavedRegs.set(AVR::R29); in determineCalleeSaves()
407 SavedRegs.set(AVR::R28); in determineCalleeSaves()
449 if ((Opcode != AVR::LDDRdPtrQ) && (Opcode != AVR::LDDWRdPtrQ) && in runOnMachineFunction()
450 (Opcode != AVR::STDPtrQRr) && (Opcode != AVR::STDWPtrQRr)) { in runOnMachineFunction()