Lines Matching refs:DstLoReg
160 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expandArith() local
168 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandArith()
171 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandArith()
172 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandArith()
193 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expandLogic() local
201 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogic()
205 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogic()
206 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLogic()
241 Register DstLoReg, DstHiReg; in expandLogicImm() local
249 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogicImm()
254 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLogicImm()
255 .addReg(DstLoReg, getKillRegState(SrcIsKill)) in expandLogicImm()
295 Register DstLoReg, DstHiReg; in expand() local
300 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
304 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
305 .addReg(DstLoReg, getKillRegState(SrcIsKill)); in expand()
349 Register DstLoReg, DstHiReg; in expand() local
359 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
363 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
364 .addReg(DstLoReg, getKillRegState(SrcIsKill)) in expand()
414 Register DstLoReg, DstHiReg; in expand() local
421 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
425 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
426 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
446 Register DstLoReg, DstHiReg; in expand() local
451 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
463 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
464 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
484 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expand() local
493 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
497 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expand()
517 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg; in expand() local
526 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
529 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expand()
552 Register DstLoReg, DstHiReg; in expand() local
557 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
561 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)); in expand()
603 Register DstLoReg, DstHiReg; in expand() local
608 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
612 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)); in expand()
649 Register DstLoReg, DstHiReg; in expand() local
656 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
662 Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg; in expand()
685 buildMI(MBB, MBBI, AVR::POPRd, DstLoReg); in expand()
698 Register DstLoReg, DstHiReg; in expand() local
705 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
711 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
731 Register DstLoReg, DstHiReg; in expand() local
738 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
750 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
764 Register DstLoReg, DstHiReg; in expand() local
772 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
782 Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg; in expand()
806 buildMI(MBB, MBBI, AVR::POPRd, DstLoReg); in expand()
818 Register DstLoReg, DstHiReg; in expandLPMWELPMW() local
825 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLPMWELPMW()
839 Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg; in expandLPMWELPMW()
861 buildMI(MBB, MBBI, AVR::POPRd, DstLoReg); in expandLPMWELPMW()
1252 Register DstLoReg, DstHiReg; in expand() local
1258 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1266 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1340 Register DstLoReg, DstHiReg; in expand() local
1345 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1348 buildMI(MBB, MBBI, OpLo, DstLoReg).setMIFlags(Flags); // Low in expand()
1423 Register DstLoReg, DstHiReg; in expand() local
1430 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1434 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1435 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expand()
1436 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
1457 Register DstLoReg, DstHiReg; in expand() local
1462 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1480 Register DstLoReg, DstHiReg; in expandLSLW4Rd() local
1485 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLSLW4Rd()
1493 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1494 .addReg(DstLoReg, RegState::Kill); in expandLSLW4Rd()
1510 .addReg(DstLoReg); in expandLSLW4Rd()
1517 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW4Rd()
1518 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLSLW4Rd()
1528 .addReg(DstLoReg); in expandLSLW4Rd()
1538 Register DstLoReg, DstHiReg; in expandLSLW8Rd() local
1543 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLSLW8Rd()
1548 .addReg(DstLoReg); in expandLSLW8Rd()
1553 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW8Rd()
1554 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLSLW8Rd()
1555 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expandLSLW8Rd()
1565 Register DstLoReg, DstHiReg; in expandLSLW12Rd() local
1570 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLSLW12Rd()
1575 .addReg(DstLoReg); in expandLSLW12Rd()
1594 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSLW12Rd()
1595 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLSLW12Rd()
1596 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expandLSLW12Rd()
1624 Register DstLoReg, DstHiReg; in expand() local
1631 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1640 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1641 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
1656 Register DstLoReg, DstHiReg; in expand() local
1661 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1666 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1667 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
1678 Register DstLoReg, DstHiReg; in expandLSRW4Rd() local
1683 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLSRW4Rd()
1691 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1692 .addReg(DstLoReg, RegState::Kill); in expandLSRW4Rd()
1697 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1698 .addReg(DstLoReg, RegState::Kill) in expandLSRW4Rd()
1706 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1707 .addReg(DstLoReg, RegState::Kill) in expandLSRW4Rd()
1724 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW4Rd()
1725 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLSRW4Rd()
1736 Register DstLoReg, DstHiReg; in expandLSRW8Rd() local
1741 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLSRW8Rd()
1745 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW8Rd()
1763 Register DstLoReg, DstHiReg; in expandLSRW12Rd() local
1768 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLSRW12Rd()
1772 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW12Rd()
1777 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW12Rd()
1778 .addReg(DstLoReg, RegState::Kill); in expandLSRW12Rd()
1783 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandLSRW12Rd()
1784 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLSRW12Rd()
1834 Register DstLoReg, DstHiReg; in expand() local
1841 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1850 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1851 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
1866 Register DstLoReg, DstHiReg; in expand() local
1871 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
1876 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
1877 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
1888 Register DstLoReg, DstHiReg; in expandASRW7Rd() local
1893 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandASRW7Rd()
1902 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW7Rd()
1903 .addReg(DstLoReg, RegState::Kill) in expandASRW7Rd()
1904 .addReg(DstLoReg, RegState::Kill); in expandASRW7Rd()
1908 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW7Rd()
1913 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW7Rd()
1914 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandASRW7Rd()
1915 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expandASRW7Rd()
1935 Register DstLoReg, DstHiReg; in expandASRW8Rd() local
1940 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandASRW8Rd()
1944 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW8Rd()
1970 Register DstLoReg, DstHiReg; in expandASRW14Rd() local
1975 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandASRW14Rd()
1991 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
1992 .addReg(DstLoReg, RegState::Kill) in expandASRW14Rd()
1993 .addReg(DstLoReg, RegState::Kill); in expandASRW14Rd()
2004 .addReg(DstLoReg); in expandASRW14Rd()
2009 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW14Rd()
2010 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandASRW14Rd()
2011 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expandASRW14Rd()
2024 Register DstLoReg, DstHiReg; in expandASRW15Rd() local
2028 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandASRW15Rd()
2053 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expandASRW15Rd()
2267 Register DstLoReg, DstHiReg; in expand() local
2286 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
2288 if (SrcReg != DstLoReg) in expand()
2290 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2297 if (SrcReg != DstLoReg && SrcIsKill) in expand()
2324 Register DstLoReg, DstHiReg; in expand() local
2338 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
2340 if (SrcReg != DstLoReg) { in expand()
2342 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()
2362 Register DstLoReg, DstHiReg; in expand() local
2368 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
2372 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead)) in expand()