134     Register DestReg = MI.getOperand(0).getReg();  in optimizeSelect()  local
136     if (!DestReg.isVirtual())  in optimizeSelect()
140                                         get(ARM::t2CSEL), DestReg)  in optimizeSelect()
152                                   const DebugLoc &DL, MCRegister DestReg,  in copyPhysReg()  argument
155   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))  in copyPhysReg()
156     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);  in copyPhysReg()
158   BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)  in copyPhysReg()
208                      Register DestReg, int FI,  in loadRegFromStackSlot()  argument
220     BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)  in loadRegFromStackSlot()
232     if (Register::isVirtualRegister(DestReg)) {  in loadRegFromStackSlot()
234       MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);  in loadRegFromStackSlot()
238     AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
239     AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
242     if (Register::isPhysicalRegister(DestReg))  in loadRegFromStackSlot()
243       MIB.addReg(DestReg, RegState::ImplicitDefine);  in loadRegFromStackSlot()
247   ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);  in loadRegFromStackSlot()
289                                   const DebugLoc &dl, Register DestReg,  in emitT2RegPlusImmediate()  argument
294   if (NumBytes == 0 && DestReg != BaseReg) {  in emitT2RegPlusImmediate()
295     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)  in emitT2RegPlusImmediate()
306   if (DestReg != ARM::SP && DestReg != BaseReg &&  in emitT2RegPlusImmediate()
312       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)  in emitT2RegPlusImmediate()
318       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)  in emitT2RegPlusImmediate()
319         .addReg(DestReg)  in emitT2RegPlusImmediate()
327         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)  in emitT2RegPlusImmediate()
329             .addReg(DestReg, RegState::Kill)  in emitT2RegPlusImmediate()
339         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)  in emitT2RegPlusImmediate()
341             .addReg(DestReg, RegState::Kill)  in emitT2RegPlusImmediate()
353     if (DestReg == ARM::SP && BaseReg != ARM::SP) {  in emitT2RegPlusImmediate()
355       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)  in emitT2RegPlusImmediate()
363     assert((DestReg != ARM::SP || BaseReg == ARM::SP) &&  in emitT2RegPlusImmediate()
367     if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) {  in emitT2RegPlusImmediate()
370       BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)  in emitT2RegPlusImmediate()
379     bool ToSP = DestReg == ARM::SP;  in emitT2RegPlusImmediate()
405     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)  in emitT2RegPlusImmediate()
413     BaseReg = DestReg;  in emitT2RegPlusImmediate()