Lines Matching refs:PostIdxReg
926 struct PostIdxRegOp PostIdxReg; member
1456 ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum); in isPostIdxRegShifted()
1459 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift; in isPostIdxReg()
3037 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); in addAM3OffsetOperands()
3038 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); in addAM3OffsetOperands()
3303 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); in addPostIdxRegOperands()
3304 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); in addPostIdxRegOperands()
3309 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); in addPostIdxRegShiftedOperands()
3312 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; in addPostIdxRegShiftedOperands()
3313 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, in addPostIdxRegShiftedOperands()
3314 PostIdxReg.ShiftTy); in addPostIdxRegShiftedOperands()
3833 Op->PostIdxReg.RegNum = RegNum; in CreatePostIdxReg()
3834 Op->PostIdxReg.isAdd = isAdd; in CreatePostIdxReg()
3835 Op->PostIdxReg.ShiftTy = ShiftTy; in CreatePostIdxReg()
3836 Op->PostIdxReg.ShiftImm = ShiftImm; in CreatePostIdxReg()
3971 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") in print()
3972 << RegName(PostIdxReg.RegNum); in print()
3973 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) in print()
3974 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " in print()
3975 << PostIdxReg.ShiftImm; in print()