Lines Matching refs:Operands
444 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
446 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
515 OperandVector &Operands);
516 bool CDEConvertDualRegOperand(StringRef Mnemonic, OperandVector &Operands);
659 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
660 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
661 bool shouldOmitVectorPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
663 void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands);
664 bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands,
708 SMLoc NameLoc, OperandVector &Operands) override;
716 OperandVector &Operands, MCStreamer &Out,
719 unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
733 SMLoc IDLoc, OperandVector &Operands);
735 OperandVector &Operands);
4142 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { in tryParseShiftRegister() argument
4168 (ARMOperand *)Operands.pop_back_val().release()); in tryParseShiftRegister()
4228 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, in tryParseShiftRegister()
4232 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, in tryParseShiftRegister()
4244 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { in tryParseRegisterWithWriteBack() argument
4252 Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc)); in tryParseRegisterWithWriteBack()
4256 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), in tryParseRegisterWithWriteBack()
4282 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), in tryParseRegisterWithWriteBack()
4341 ARMAsmParser::parseITCondCode(OperandVector &Operands) { in parseITCondCode() argument
4352 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); in parseITCondCode()
4361 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { in parseCoprocNumOperand() argument
4375 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); in parseCoprocNumOperand()
4383 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { in parseCoprocRegOperand() argument
4395 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); in parseCoprocRegOperand()
4402 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { in parseCoprocOptionOperand() argument
4430 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); in parseCoprocOptionOperand()
4475 bool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder, in parseRegisterList() argument
4633 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); in parseRegisterList()
4637 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); in parseRegisterList()
4698 ARMAsmParser::parseVectorList(OperandVector &Operands) { in parseVectorList() argument
4717 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); in parseVectorList()
4720 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, in parseVectorList()
4724 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, in parseVectorList()
4740 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); in parseVectorList()
4745 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, in parseVectorList()
4749 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, in parseVectorList()
4940 Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E)); in parseVectorList()
4944 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, in parseVectorList()
4955 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { in parseMemBarrierOptOperand() argument
5021 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); in parseMemBarrierOptOperand()
5026 ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) { in parseTraceSyncBarrierOptOperand() argument
5039 Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S)); in parseTraceSyncBarrierOptOperand()
5045 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { in parseInstSyncBarrierOptOperand() argument
5089 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( in parseInstSyncBarrierOptOperand()
5097 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { in parseProcIFlagsOperand() argument
5126 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); in parseProcIFlagsOperand()
5132 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { in parseMSRMaskOperand() argument
5144 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); in parseMSRMaskOperand()
5160 Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); in parseMSRMaskOperand()
5223 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); in parseMSRMaskOperand()
5230 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { in parseBankedRegOperand() argument
5244 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S)); in parseBankedRegOperand()
5249 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low, in parsePKHImm() argument
5292 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); in parsePKHImm()
5298 ARMAsmParser::parseSetEndImm(OperandVector &Operands) { in parseSetEndImm() argument
5316 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val, in parseSetEndImm()
5328 ARMAsmParser::parseShifterImm(OperandVector &Operands) { in parseShifterImm() argument
5390 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); in parseShifterImm()
5399 ARMAsmParser::parseRotImm(OperandVector &Operands) { in parseRotImm() argument
5440 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); in parseRotImm()
5446 ARMAsmParser::parseModImm(OperandVector &Operands) { in parseModImm() argument
5493 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF), in parseModImm()
5506 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); in parseModImm()
5512 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); in parseModImm()
5551 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2)); in parseModImm()
5563 ARMAsmParser::parseBitfield(OperandVector &Operands) { in parseBitfield() argument
5626 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); in parseBitfield()
5632 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) { in parsePostIdxReg() argument
5675 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, in parsePostIdxReg()
5682 ARMAsmParser::parseAM3Offset(OperandVector &Operands) { in parseAM3Offset() argument
5720 Operands.push_back( in parseAM3Offset()
5746 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, in parseAM3Offset()
5756 const OperandVector &Operands) { in cvtThumbMultiply() argument
5757 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5758 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1); in cvtThumbMultiply()
5762 if (Operands.size() == 6 && in cvtThumbMultiply()
5763 ((ARMOperand &)*Operands[4]).getReg() == in cvtThumbMultiply()
5764 ((ARMOperand &)*Operands[3]).getReg()) in cvtThumbMultiply()
5766 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5768 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2); in cvtThumbMultiply()
5772 const OperandVector &Operands) { in cvtThumbBranches() argument
5795 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); in cvtThumbBranches()
5812 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
5819 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
5825 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); in cvtThumbBranches()
5826 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2); in cvtThumbBranches()
5830 MCInst &Inst, const OperandVector &Operands) { in cvtMVEVMOVQtoDReg() argument
5833 assert(Operands.size() == 8); in cvtMVEVMOVQtoDReg()
5835 ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt in cvtMVEVMOVQtoDReg()
5836 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2 in cvtMVEVMOVQtoDReg()
5837 ((ARMOperand &)*Operands[4]).addRegOperands(Inst, 1); // Qd in cvtMVEVMOVQtoDReg()
5838 ((ARMOperand &)*Operands[5]).addMVEPairVectorIndexOperands(Inst, 1); // idx in cvtMVEVMOVQtoDReg()
5840 ((ARMOperand &)*Operands[7]).addMVEPairVectorIndexOperands(Inst, 1); // idx2 in cvtMVEVMOVQtoDReg()
5841 ((ARMOperand &)*Operands[1]).addCondCodeOperands(Inst, 2); // condition code in cvtMVEVMOVQtoDReg()
5846 bool ARMAsmParser::parseMemory(OperandVector &Operands) { in parseMemory() argument
5869 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, in parseMemory()
5876 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
5926 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, in parseMemory()
5933 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
5969 Operands.push_back(ARMOperand::CreateMem( in parseMemory()
5981 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
6018 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum, in parseMemory()
6025 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
6100 ARMAsmParser::parseFPImm(OperandVector &Operands) { in parseFPImm() argument
6127 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]); in parseFPImm()
6131 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]); in parseFPImm()
6153 Operands.push_back(ARMOperand::CreateImm( in parseFPImm()
6170 Operands.push_back(ARMOperand::CreateImm( in parseFPImm()
6182 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { in parseOperand() argument
6188 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); in parseOperand()
6207 if (!tryParseRegisterWithWriteBack(Operands)) in parseOperand()
6209 int Res = tryParseShiftRegister(Operands); in parseOperand()
6219 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); in parseOperand()
6239 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); in parseOperand()
6243 return parseMemory(Operands); in parseOperand()
6245 return parseRegisterList(Operands, !Mnemonic.startswith("clr")); in parseOperand()
6280 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); in parseOperand()
6286 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), in parseOperand()
6311 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); in parseOperand()
6326 Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E)); in parseOperand()
6656 OperandVector &Operands) { in tryConvertingToTwoOperandForm() argument
6657 if (Operands.size() != 6) in tryConvertingToTwoOperandForm()
6660 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]); in tryConvertingToTwoOperandForm()
6661 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); in tryConvertingToTwoOperandForm()
6672 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); in tryConvertingToTwoOperandForm()
6732 Operands.erase(Operands.begin() + 3); in tryConvertingToTwoOperandForm()
6737 OperandVector &Operands) { in shouldOmitCCOutOperand() argument
6749 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && in shouldOmitCCOutOperand()
6750 !static_cast<ARMOperand &>(*Operands[4]).isModImm() && in shouldOmitCCOutOperand()
6751 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() && in shouldOmitCCOutOperand()
6752 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) in shouldOmitCCOutOperand()
6757 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && in shouldOmitCCOutOperand()
6758 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6759 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
6760 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) in shouldOmitCCOutOperand()
6768 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6769 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
6770 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
6771 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
6772 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) || in shouldOmitCCOutOperand()
6773 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4())) in shouldOmitCCOutOperand()
6781 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6782 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
6783 static_cast<ARMOperand &>(*Operands[5]).isImm()) { in shouldOmitCCOutOperand()
6789 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && in shouldOmitCCOutOperand()
6790 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && in shouldOmitCCOutOperand()
6791 static_cast<ARMOperand &>(*Operands[5]).isImm0_7()) in shouldOmitCCOutOperand()
6795 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && in shouldOmitCCOutOperand()
6796 (static_cast<ARMOperand &>(*Operands[5]).isT2SOImm() || in shouldOmitCCOutOperand()
6797 static_cast<ARMOperand &>(*Operands[5]).isT2SOImmNeg())) in shouldOmitCCOutOperand()
6808 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && in shouldOmitCCOutOperand()
6809 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
6810 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6811 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
6812 static_cast<ARMOperand &>(*Operands[5]).isReg() && in shouldOmitCCOutOperand()
6817 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || in shouldOmitCCOutOperand()
6818 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || in shouldOmitCCOutOperand()
6819 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || in shouldOmitCCOutOperand()
6820 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() != in shouldOmitCCOutOperand()
6821 static_cast<ARMOperand &>(*Operands[5]).getReg() && in shouldOmitCCOutOperand()
6822 static_cast<ARMOperand &>(*Operands[3]).getReg() != in shouldOmitCCOutOperand()
6823 static_cast<ARMOperand &>(*Operands[4]).getReg()))) in shouldOmitCCOutOperand()
6828 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && in shouldOmitCCOutOperand()
6829 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
6830 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6831 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
6835 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || in shouldOmitCCOutOperand()
6836 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || in shouldOmitCCOutOperand()
6846 (Operands.size() == 5 || Operands.size() == 6) && in shouldOmitCCOutOperand()
6847 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6848 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
6849 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
6850 (static_cast<ARMOperand &>(*Operands[4]).isImm() || in shouldOmitCCOutOperand()
6851 (Operands.size() == 6 && in shouldOmitCCOutOperand()
6852 static_cast<ARMOperand &>(*Operands[5]).isImm()))) { in shouldOmitCCOutOperand()
6855 (static_cast<ARMOperand &>(*Operands[4]).isT2SOImm() || in shouldOmitCCOutOperand()
6856 static_cast<ARMOperand &>(*Operands[4]).isT2SOImmNeg()))); in shouldOmitCCOutOperand()
6862 (Operands.size() == 5) && in shouldOmitCCOutOperand()
6863 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
6864 static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::SP && in shouldOmitCCOutOperand()
6865 static_cast<ARMOperand &>(*Operands[3]).getReg() != ARM::PC && in shouldOmitCCOutOperand()
6866 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
6867 static_cast<ARMOperand &>(*Operands[4]).isImm()) { in shouldOmitCCOutOperand()
6868 const ARMOperand &IMM = static_cast<ARMOperand &>(*Operands[4]); in shouldOmitCCOutOperand()
6875 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg())) in shouldOmitCCOutOperand()
6884 OperandVector &Operands) { in shouldOmitPredicateOperand() argument
6889 (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" || in shouldOmitPredicateOperand()
6890 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) { in shouldOmitPredicateOperand()
6891 if (static_cast<ARMOperand &>(*Operands[3]).isToken() && in shouldOmitPredicateOperand()
6892 (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" || in shouldOmitPredicateOperand()
6893 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16")) in shouldOmitPredicateOperand()
6896 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && in shouldOmitPredicateOperand()
6898 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || in shouldOmitPredicateOperand()
6900 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()))) in shouldOmitPredicateOperand()
6907 OperandVector &Operands) { in shouldOmitVectorPredicateOperand() argument
6908 if (!hasMVE() || Operands.size() < 3) in shouldOmitVectorPredicateOperand()
6921 for (auto &Operand : Operands) { in shouldOmitVectorPredicateOperand()
6933 for (auto &Operand : Operands) { in shouldOmitVectorPredicateOperand()
6976 OperandVector &Operands) { in fixupGNULDRDAlias() argument
6979 if (Operands.size() < 4) in fixupGNULDRDAlias()
6982 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]); in fixupGNULDRDAlias()
6983 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); in fixupGNULDRDAlias()
7007 Operands.insert( in fixupGNULDRDAlias()
7008 Operands.begin() + 3, in fixupGNULDRDAlias()
7018 OperandVector &Operands) { in CDEConvertDualRegOperand() argument
7024 if (Operands.size() <= 3 + NumPredOps) in CDEConvertDualRegOperand()
7030 const MCParsedAsmOperand &Op2 = *Operands[2 + NumPredOps]; in CDEConvertDualRegOperand()
7065 const MCParsedAsmOperand &Op3 = *Operands[3 + NumPredOps]; in CDEConvertDualRegOperand()
7069 Operands.erase(Operands.begin() + 3 + NumPredOps); in CDEConvertDualRegOperand()
7070 Operands[2 + NumPredOps] = in CDEConvertDualRegOperand()
7077 SMLoc NameLoc, OperandVector &Operands) { in ParseInstruction() argument
7117 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); in ParseInstruction()
7149 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); in ParseInstruction()
7189 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, in ParseInstruction()
7197 Operands.push_back(ARMOperand::CreateCondCode( in ParseInstruction()
7214 Operands.push_back(ARMOperand::CreateVPTPred( in ParseInstruction()
7220 Operands.push_back(ARMOperand::CreateImm( in ParseInstruction()
7251 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); in ParseInstruction()
7258 if (parseOperand(Operands, Mnemonic)) { in ParseInstruction()
7264 if (parseOperand(Operands, Mnemonic)) { in ParseInstruction()
7273 tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands); in ParseInstruction()
7284 bool GotError = CDEConvertDualRegOperand(Mnemonic, Operands); in ParseInstruction()
7297 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) in ParseInstruction()
7298 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7305 shouldOmitPredicateOperand(Mnemonic, Operands)) in ParseInstruction()
7306 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7310 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands) && in ParseInstruction()
7315 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7316 Operands.erase(Operands.begin()); in ParseInstruction()
7320 Operands.insert(Operands.begin(), in ParseInstruction()
7322 Operands.insert(Operands.begin(), in ParseInstruction()
7325 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { in ParseInstruction()
7330 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7331 Operands.erase(Operands.begin()); in ParseInstruction()
7335 Operands.insert(Operands.begin(), in ParseInstruction()
7337 Operands.insert(Operands.begin(), in ParseInstruction()
7340 !shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { in ParseInstruction()
7344 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7345 Operands.erase(Operands.begin()); in ParseInstruction()
7347 Operands.insert(Operands.begin(), in ParseInstruction()
7359 if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { in ParseInstruction()
7366 if (Mnemonic.startswith("vcvtt") && Operands.size() >= 4) { in ParseInstruction()
7367 auto Sz1 = static_cast<ARMOperand &>(*Operands[2]); in ParseInstruction()
7368 auto Sz2 = static_cast<ARMOperand &>(*Operands[3]); in ParseInstruction()
7371 Operands.erase(Operands.begin()); in ParseInstruction()
7376 Operands.insert(Operands.begin(), in ParseInstruction()
7380 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7383 Operands.insert(Operands.begin() + 1, in ParseInstruction()
7391 if (shouldOmitVectorPredicateOperand(Mnemonic, Operands)) { in ParseInstruction()
7393 Operands.erase(Operands.begin() + 2); in ParseInstruction()
7395 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7397 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7404 for (unsigned I = 1; I < Operands.size(); ++I) in ParseInstruction()
7405 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred()) in ParseInstruction()
7416 Operands.erase(Operands.begin()); in ParseInstruction()
7417 Operands.insert(Operands.begin(), in ParseInstruction()
7427 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && in ParseInstruction()
7428 static_cast<ARMOperand &>(*Operands[2]).isImm()) in ParseInstruction()
7429 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7438 if (!isThumb() && Operands.size() > 4 && in ParseInstruction()
7443 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]); in ParseInstruction()
7444 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]); in ParseInstruction()
7463 Operands[Idx] = in ParseInstruction()
7465 Operands.erase(Operands.begin() + Idx + 1); in ParseInstruction()
7470 fixupGNULDRDAlias(Mnemonic, Operands); in ParseInstruction()
7477 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 && in ParseInstruction()
7478 static_cast<ARMOperand &>(*Operands[3]).isReg() && in ParseInstruction()
7479 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC && in ParseInstruction()
7480 static_cast<ARMOperand &>(*Operands[4]).isReg() && in ParseInstruction()
7481 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR && in ParseInstruction()
7482 static_cast<ARMOperand &>(*Operands[5]).isImm()) { in ParseInstruction()
7483 Operands.front() = ARMOperand::CreateToken(Name, NameLoc); in ParseInstruction()
7484 Operands.erase(Operands.begin() + 1); in ParseInstruction()
7530 const OperandVector &Operands, in validatetLDMRegList() argument
7532 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); in validatetLDMRegList()
7540 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetLDMRegList()
7543 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetLDMRegList()
7549 const OperandVector &Operands, in validatetSTMRegList() argument
7551 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); in validatetSTMRegList()
7558 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetSTMRegList()
7561 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetSTMRegList()
7564 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetSTMRegList()
7570 const OperandVector &Operands, in validateLDRDSTRD() argument
7579 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7584 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7590 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7593 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7603 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7612 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7616 return Error(Operands[3]->getStartLoc(), in validateLDRDSTRD()
7641 const OperandVector &Operands) { in validateInstruction() argument
7643 SMLoc Loc = Operands[0]->getStartLoc(); in validateInstruction()
7657 for (unsigned I = 1; I < Operands.size(); ++I) in validateInstruction()
7658 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode()) in validateInstruction()
7659 CondLoc = Operands[I]->getStartLoc(); in validateInstruction()
7704 for (unsigned I = 1; I < Operands.size(); ++I) in validateInstruction()
7705 if (static_cast<ARMOperand &>(*Operands[I]).isVPTPred()) in validateInstruction()
7706 PredLoc = Operands[I]->getStartLoc(); in validateInstruction()
7735 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true, in validateInstruction()
7741 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/true, in validateInstruction()
7746 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false, in validateInstruction()
7752 if (validateLDRDSTRD(Inst, Operands, /*Load*/true, /*ARMMode*/false, in validateInstruction()
7760 return Error(Operands[2]->getStartLoc(), in validateInstruction()
7765 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true, in validateInstruction()
7771 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/true, in validateInstruction()
7777 if (validateLDRDSTRD(Inst, Operands, /*Load*/false, /*ARMMode*/false, in validateInstruction()
7802 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7815 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7821 return Error(Operands[5]->getStartLoc(), in validateInstruction()
7827 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7862 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7906 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7922 return Error(Operands[5]->getStartLoc(), in validateInstruction()
7936 (static_cast<ARMOperand &>(*Operands[3]).isToken() && in validateInstruction()
7937 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); in validateInstruction()
7940 return Error(Operands[3 + HasWritebackToken]->getStartLoc(), in validateInstruction()
7944 return Error(Operands[2]->getStartLoc(), in validateInstruction()
7949 return Error(Operands[3]->getStartLoc(), in validateInstruction()
7953 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
7966 return Error(Operands.back()->getStartLoc(), in validateInstruction()
7971 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
7976 if (validatetSTMRegList(Inst, Operands, 3)) in validateInstruction()
7984 return Error(Operands.back()->getStartLoc(), in validateInstruction()
7988 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
7991 if (validatetSTMRegList(Inst, Operands, 3)) in validateInstruction()
8001 return Error(Operands[4]->getStartLoc(), in validateInstruction()
8009 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8020 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() != in validateInstruction()
8021 ((ARMOperand &)*Operands[5]).getReg()) && in validateInstruction()
8022 (((ARMOperand &)*Operands[3]).getReg() != in validateInstruction()
8023 ((ARMOperand &)*Operands[4]).getReg())) { in validateInstruction()
8024 return Error(Operands[3]->getStartLoc(), in validateInstruction()
8036 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8038 if (validatetLDMRegList(Inst, Operands, 2, !isMClass())) in validateInstruction()
8046 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8048 if (validatetSTMRegList(Inst, Operands, 2)) in validateInstruction()
8057 return Error(Operands[4]->getStartLoc(), in validateInstruction()
8063 return Error(Operands[4]->getStartLoc(), in validateInstruction()
8067 if (validatetSTMRegList(Inst, Operands, 4)) in validateInstruction()
8076 return Error(Operands[4]->getStartLoc(), in validateInstruction()
8087 return Error(Operands[4]->getStartLoc(), in validateInstruction()
8093 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>()) in validateInstruction()
8094 return Error(Operands[2]->getStartLoc(), "branch target out of range"); in validateInstruction()
8097 int op = (Operands[2]->isImm()) ? 2 : 3; in validateInstruction()
8098 ARMOperand &Operand = static_cast<ARMOperand &>(*Operands[op]); in validateInstruction()
8102 return Error(Operands[op]->getStartLoc(), "branch target out of range"); in validateInstruction()
8107 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>()) in validateInstruction()
8108 return Error(Operands[2]->getStartLoc(), "branch target out of range"); in validateInstruction()
8111 int Op = (Operands[2]->isImm()) ? 2 : 3; in validateInstruction()
8112 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>()) in validateInstruction()
8113 return Error(Operands[Op]->getStartLoc(), "branch target out of range"); in validateInstruction()
8118 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>()) in validateInstruction()
8119 return Error(Operands[2]->getStartLoc(), "branch target out of range"); in validateInstruction()
8133 int i = (Operands[3]->isImm()) ? 3 : 4; in validateInstruction()
8134 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]); in validateInstruction()
8154 return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not " in validateInstruction()
8158 return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not " in validateInstruction()
8167 if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<4, 1>() || in validateInstruction()
8169 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8173 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<16, 1>()) in validateInstruction()
8174 return Error(Operands[3]->getStartLoc(), in validateInstruction()
8177 if (!static_cast<ARMOperand &>(*Operands[3]).isSignedOffset<18, 1>()) in validateInstruction()
8178 return Error(Operands[3]->getStartLoc(), in validateInstruction()
8184 if (!static_cast<ARMOperand &>(*Operands[1]).isUnsignedOffset<4, 1>() || in validateInstruction()
8186 return Error(Operands[1]->getStartLoc(), in validateInstruction()
8189 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<16, 1>()) in validateInstruction()
8190 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8201 Operands[3]->getStartLoc(), in validateInstruction()
8211 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8229 return Error(Operands[1]->getStartLoc(), in validateInstruction()
8233 return Error(Operands[1]->getStartLoc(), in validateInstruction()
8243 return Error(Operands[5]->getStartLoc(), in validateInstruction()
8252 return Error(Operands[3]->getStartLoc(), in validateInstruction()
8258 ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]); in validateInstruction()
8261 return Error(Operands[3]->getStartLoc(), in validateInstruction()
8272 if (Operands[3]->getReg() == Operands[4]->getReg()) { in validateInstruction()
8273 return Error (Operands[3]->getStartLoc(), in validateInstruction()
8276 if (Operands[3]->getReg() == Operands[5]->getReg()) { in validateInstruction()
8277 return Error (Operands[3]->getStartLoc(), in validateInstruction()
8283 if (Operands[4]->getReg() != Operands[6]->getReg()) in validateInstruction()
8284 return Error (Operands[4]->getStartLoc(), "Q-registers must be the same"); in validateInstruction()
8285 if (static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() != in validateInstruction()
8286 static_cast<ARMOperand &>(*Operands[7]).getVectorIndex() + 2) in validateInstruction()
8287 return Error (Operands[5]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1"); in validateInstruction()
8291 if (Operands[2]->getReg() != Operands[4]->getReg()) in validateInstruction()
8292 return Error (Operands[2]->getStartLoc(), "Q-registers must be the same"); in validateInstruction()
8293 if (static_cast<ARMOperand &>(*Operands[3]).getVectorIndex() != in validateInstruction()
8294 static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() + 2) in validateInstruction()
8295 return Error (Operands[3]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1"); in validateInstruction()
8367 return Error(Operands[1]->getStartLoc(), in validateInstruction()
8370 return Error(Operands[1]->getStartLoc(), in validateInstruction()
8430 return Error(Operands[2]->getStartLoc(), in validateInstruction()
8696 const OperandVector &Operands, in processInstruction() argument
8701 for (auto &Op : Operands) { in processInstruction()
8868 static_cast<ARMOperand &>(*Operands[4]) : in processInstruction()
8869 static_cast<ARMOperand &>(*Operands[3])); in processInstruction()
10231 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" && in processInstruction()
10249 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" && in processInstruction()
10268 const StringRef Token = static_cast<ARMOperand &>(*Operands[0]).getToken(); in processInstruction()
10295 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { in processInstruction()
10305 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { in processInstruction()
10425 (static_cast<ARMOperand &>(*Operands[3]).isToken() && in processInstruction()
10426 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); in processInstruction()
10868 unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst, in MatchInstruction() argument
10875 return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm); in MatchInstruction()
10881 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) == in MatchInstruction()
10907 MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm); in MatchInstruction()
10934 if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) == in MatchInstruction()
10958 OperandVector &Operands, in MatchAndEmitInstruction() argument
10966 MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm, in MatchAndEmitInstruction()
10977 if (validateInstruction(Inst, Operands)) { in MatchAndEmitInstruction()
10990 while (processInstruction(Inst, Operands, Out)) in MatchAndEmitInstruction()
11017 ReportNearMisses(NearMisses, IDLoc, Operands); in MatchAndEmitInstruction()
11022 ((ARMOperand &)*Operands[0]).getToken(), FBS); in MatchAndEmitInstruction()
11024 ((ARMOperand &)*Operands[0]).getLocRange()); in MatchAndEmitInstruction()
11726 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; in parseDirectiveRegSave() local
11729 if (parseRegisterList(Operands, true, true) || parseEOL()) in parseDirectiveRegSave()
11731 ARMOperand &Op = (ARMOperand &)*Operands[0]; in parseDirectiveRegSave()
12073 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; in parseDirectiveSEHSaveRegs() local
12075 if (parseRegisterList(Operands) || parseEOL()) in parseDirectiveSEHSaveRegs()
12077 ARMOperand &Op = (ARMOperand &)*Operands[0]; in parseDirectiveSEHSaveRegs()
12115 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; in parseDirectiveSEHSaveFRegs() local
12117 if (parseRegisterList(Operands) || parseEOL()) in parseDirectiveSEHSaveFRegs()
12119 ARMOperand &Op = (ARMOperand &)*Operands[0]; in parseDirectiveSEHSaveFRegs()
12271 SMLoc IDLoc, OperandVector &Operands) { in FilterNearMisses() argument
12294 ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc(); in FilterNearMisses()
12408 SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc(); in FilterNearMisses()
12424 SMLoc IDLoc, OperandVector &Operands) { in ReportNearMisses() argument
12426 FilterNearMisses(NearMisses, Messages, IDLoc, Operands); in ReportNearMisses()