408     addPass(createLowerAtomicPass());  in addIRPasses()
410     addPass(createAtomicExpandPass());  in addIRPasses()
416     addPass(createCFGSimplificationPass(  in addIRPasses()
423   addPass(createMVEGatherScatterLoweringPass());  in addIRPasses()
424   addPass(createMVELaneInterleavingPass());  in addIRPasses()
430     addPass(createARMParallelDSPPass());  in addIRPasses()
434     addPass(createInterleavedAccessPass());  in addIRPasses()
438     addPass(createCFGuardCheckPass());  in addIRPasses()
441     addPass(createJMCInstrumenterPass());  in addIRPasses()
446     addPass(createTypePromotionPass());  in addCodeGenPrepare()
466     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,  in addPreISel()
471     addPass(createHardwareLoopsPass());  in addPreISel()
472     addPass(createMVETailPredicationPass());  in addPreISel()
480     addPass(createBarrierNoopPass());  in addPreISel()
487   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));  in addInstSelector()
492   addPass(new IRTranslator(getOptLevel()));  in addIRTranslator()
497   addPass(new Legalizer());  in addLegalizeMachineIR()
502   addPass(new RegBankSelect());  in addRegBankSelect()
507   addPass(new InstructionSelect(getOptLevel()));  in addGlobalInstructionSelect()
514       addPass(&MachinePipelinerID);  in addPreRegAlloc()
516     addPass(createMVETPAndVPTOptimisationsPass());  in addPreRegAlloc()
518     addPass(createMLxExpansionPass());  in addPreRegAlloc()
521       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));  in addPreRegAlloc()
524       addPass(createA15SDOptimizerPass());  in addPreRegAlloc()
531       addPass(createARMLoadStoreOptimizationPass());  in addPreSched2()
533     addPass(new ARMExecutionDomainFix());  in addPreSched2()
534     addPass(createBreakFalseDeps());  in addPreSched2()
539   addPass(createARMExpandPseudoPass());  in addPreSched2()
545     addPass(createThumb2SizeReductionPass([this](const Function &F) {  in addPreSched2()
550     addPass(createIfConverter([](const MachineFunction &MF) {  in addPreSched2()
554   addPass(createThumb2ITBlockPass());  in addPreSched2()
559     addPass(&PostMachineSchedulerID);  in addPreSched2()
560     addPass(&PostRASchedulerID);  in addPreSched2()
563   addPass(createMVEVPTBlockPass());  in addPreSched2()
564   addPass(createARMIndirectThunks());  in addPreSched2()
565   addPass(createARMSLSHardeningPass());  in addPreSched2()
569   addPass(createThumb2SizeReductionPass());  in addPreEmitPass()
572   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {  in addPreEmitPass()
578     addPass(createARMBlockPlacementPass());  in addPreEmitPass()
579     addPass(createARMOptimizeBarriersPass());  in addPreEmitPass()
587   addPass(createARMFixCortexA57AES1742098Pass());  in addPreEmitPass2()
590   addPass(createARMBranchTargetsPass());  in addPreEmitPass2()
594   addPass(createARMConstantIslandPass());  in addPreEmitPass2()
598   addPass(createARMLowOverheadLoopsPass());  in addPreEmitPass2()
602     addPass(createCFGuardLongjmpPass());  in addPreEmitPass2()
604     addPass(createEHContGuardCatchretPass());  in addPreEmitPass2()