141     const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);  in ARMRegisterBankInfo()  local
142     (void)RBGPR;  in ARMRegisterBankInfo()
143     assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");  in ARMRegisterBankInfo()
146     assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&  in ARMRegisterBankInfo()
148     assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&  in ARMRegisterBankInfo()
150     assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) &&  in ARMRegisterBankInfo()
152     assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) &&  in ARMRegisterBankInfo()
154     assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) &&  in ARMRegisterBankInfo()
156     assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) &&  in ARMRegisterBankInfo()
158     assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnoip_and_tcGPRRegClassID)) &&  in ARMRegisterBankInfo()
160     assert(RBGPR.covers(*TRI.getRegClass(  in ARMRegisterBankInfo()
163     assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPROdd_and_tcGPRRegClassID)) &&  in ARMRegisterBankInfo()
165     assert(RBGPR.getSize() == 32 && "GPRs should hold up to 32-bit");  in ARMRegisterBankInfo()