Lines Matching refs:isT2
1787 bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8; in FixInvalidRegPairOp() local
1797 assert((isT2 || MI->getOperand(3).getReg() == ARM::NoRegister) && in FixInvalidRegPairOp()
1807 ? (isT2 ? ARM::t2LDMIA : ARM::LDMIA) in FixInvalidRegPairOp()
1808 : (isT2 ? ARM::t2STMIA : ARM::STMIA); in FixInvalidRegPairOp()
1831 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1832 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
1836 ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12) in FixInvalidRegPairOp()
1837 : (isT2 ? (OffImm+4 < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12); in FixInvalidRegPairOp()
2174 ARMCC::CondCodes &Pred, bool &isT2);
2259 Register &PredReg, ARMCC::CondCodes &Pred, bool &isT2) { in CanFormLdStDWord() argument
2274 isT2 = true; in CanFormLdStDWord()
2278 isT2 = true; in CanFormLdStDWord()
2301 if (isT2) { in CanFormLdStDWord()
2423 bool isT2 = false; in RescheduleOps() local
2429 Offset, PredReg, Pred, isT2)) { in RescheduleOps()
2447 if (!isT2) in RescheduleOps()
2461 if (!isT2) in RescheduleOps()
2471 if (!isT2) { in RescheduleOps()