1523   bool isLd = isLoadSingle(Opcode);  in MergeBaseUpdateLoadStore()  local
1532                    .addReg(Base, getKillRegState(isLd ? BaseKill : false))  in MergeBaseUpdateLoadStore()
1535                    .addReg(MO.getReg(), (isLd ? getDefRegState(true)  in MergeBaseUpdateLoadStore()
1540   } else if (isLd) {  in MergeBaseUpdateLoadStore()
1788   bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;  in FixInvalidRegPairOp()  local
1789   bool EvenDeadKill = isLd ?  in FixInvalidRegPairOp()
1792   bool OddDeadKill  = isLd ?  in FixInvalidRegPairOp()
1806     unsigned NewOpc = (isLd)  in FixInvalidRegPairOp()
1809     if (isLd) {  in FixInvalidRegPairOp()
1813         .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))  in FixInvalidRegPairOp()
1814         .addReg(OddReg,  getDefRegState(isLd) | getDeadRegState(OddDeadKill))  in FixInvalidRegPairOp()
1830     unsigned NewOpc = (isLd)  in FixInvalidRegPairOp()
1835     unsigned NewOpc2 = (isLd)  in FixInvalidRegPairOp()
1840     if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) {  in FixInvalidRegPairOp()
1842       InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill,  in FixInvalidRegPairOp()
1844       InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,  in FixInvalidRegPairOp()
1858       InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,  in FixInvalidRegPairOp()
1861       InsertLDR_STR(MBB, MBBI, OffImm + 4, isLd, NewOpc2, OddReg, OddDeadKill,  in FixInvalidRegPairOp()
1865     if (isLd)  in FixInvalidRegPairOp()
2177                        unsigned Base, bool isLd,
2219 static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base,  in IsSafeAndProfitableToMove()  argument
2233     if (I->mayStore() || (!isLd && I->mayLoad()))  in IsSafeAndProfitableToMove()
2329                                  unsigned Base, bool isLd,  in RescheduleOps()  argument
2404         DoMove = IsSafeAndProfitableToMove(isLd, Base, FirstOp, LastOp,  in RescheduleOps()
2411         MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp;  in RescheduleOps()
2439           if (isLd) {  in RescheduleOps()
2527       bool isLd = isLoadSingle(Opc);  in RescheduleLoadStoreInstrs()  local
2548       if (isLd)  in RescheduleLoadStoreInstrs()