Lines Matching refs:EvenReg

1771   Register EvenReg = MI->getOperand(0).getReg();  in FixInvalidRegPairOp()  local
1773   unsigned EvenRegNum = TRI->getDwarfRegNum(EvenReg, false);  in FixInvalidRegPairOp()
1778   bool Errata602117 = EvenReg == BaseReg &&  in FixInvalidRegPairOp()
1813         .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))  in FixInvalidRegPairOp()
1821         .addReg(EvenReg,  in FixInvalidRegPairOp()
1840     if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) {  in FixInvalidRegPairOp()
1844       InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,  in FixInvalidRegPairOp()
1848       if (OddReg == EvenReg && EvenDeadKill) {  in FixInvalidRegPairOp()
1856       if (EvenReg == BaseReg)  in FixInvalidRegPairOp()
1858       InsertLDR_STR(MBB, MBBI, OffImm, isLd, NewOpc, EvenReg, EvenDeadKill,  in FixInvalidRegPairOp()
2172                           unsigned &NewOpc, Register &EvenReg, Register &OddReg,