Lines Matching refs:Sd
159 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
160 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
161 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]>,
169 def VLDRH : AHI5<0b1101, 0b01, (outs HPR:$Sd), (ins addrmode5fp16:$addr),
170 IIC_fpLoad16, "vldr", ".16\t$Sd, $addr",
171 [(set HPR:$Sd, (f16 (alignedload16 addrmode5fp16:$addr)))]>,
194 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
195 IIC_fpStore32, "vstr", "\t$Sd, $addr",
196 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]>,
204 def VSTRH : AHI5<0b1101, 0b00, (outs), (ins HPR:$Sd, addrmode5fp16:$addr),
205 IIC_fpStore16, "vstr", ".16\t$Sd, $addr",
206 [(alignedstore16 (f16 HPR:$Sd), addrmode5fp16:$addr)]>,
209 def : Pat<(alignedstore16 (bf16 HPR:$Sd), addrmode5fp16:$addr),
210 (VSTRH (bf16 HPR:$Sd), addrmode5fp16:$addr)> {
213 def : Pat<(alignedstore16 (bf16 HPR:$Sd), addrmode3:$addr),
214 (STRH (COPY_TO_REGCLASS $Sd, GPR), addrmode3:$addr)> {
217 def : Pat<(alignedstore16 (bf16 HPR:$Sd), t2addrmode_imm12:$addr),
218 (t2STRHi12 (COPY_TO_REGCLASS $Sd, GPR), t2addrmode_imm12:$addr)> {
410 let TwoOperandAliasConstraint = "$Sn = $Sd" in
412 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
413 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
414 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>,
421 let TwoOperandAliasConstraint = "$Sn = $Sd" in
423 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
424 IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm",
425 [(set (f16 HPR:$Sd), (fadd (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
435 let TwoOperandAliasConstraint = "$Sn = $Sd" in
437 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
438 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
439 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>,
446 let TwoOperandAliasConstraint = "$Sn = $Sd" in
448 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
449 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm",
450 [(set (f16 HPR:$Sd), (fsub (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
460 let TwoOperandAliasConstraint = "$Sn = $Sd" in
462 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
463 IIC_fpDIV32, "vdiv", ".f32\t$Sd, $Sn, $Sm",
464 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>,
467 let TwoOperandAliasConstraint = "$Sn = $Sd" in
469 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
470 IIC_fpDIV16, "vdiv", ".f16\t$Sd, $Sn, $Sm",
471 [(set (f16 HPR:$Sd), (fdiv (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
481 let TwoOperandAliasConstraint = "$Sn = $Sd" in
483 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
484 IIC_fpMUL32, "vmul", ".f32\t$Sd, $Sn, $Sm",
485 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>,
492 let TwoOperandAliasConstraint = "$Sn = $Sd" in
494 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
495 IIC_fpMUL16, "vmul", ".f16\t$Sd, $Sn, $Sm",
496 [(set (f16 HPR:$Sd), (fmul (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
506 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
507 IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
508 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>,
516 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
517 IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm",
518 [(set (f16 HPR:$Sd), (fneg (fmul (f16 HPR:$Sn), (f16 HPR:$Sm))))]>,
525 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
526 NoItinerary, !strconcat("vsel", op, ".f16\t$Sd, $Sn, $Sm"),
527 [(set (f16 HPR:$Sd), (ARMcmov (f16 HPR:$Sm), (f16 HPR:$Sn), CC))]>,
531 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
532 NoItinerary, !strconcat("vsel", op, ".f32\t$Sd, $Sn, $Sm"),
533 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
554 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
555 NoItinerary, !strconcat(op, ".f16\t$Sd, $Sn, $Sm"),
556 [(set (f16 HPR:$Sd), (SD (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
560 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
561 NoItinerary, !strconcat(op, ".f32\t$Sd, $Sn, $Sm"),
562 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
591 (outs), (ins SPR:$Sd, SPR:$Sm),
592 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", "",
593 [(arm_cmpfpe SPR:$Sd, SPR:$Sm)]> {
600 (outs), (ins HPR:$Sd, HPR:$Sm),
601 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm",
602 [(arm_cmpfpe (f16 HPR:$Sd), (f16 HPR:$Sm))]>;
610 (outs), (ins SPR:$Sd, SPR:$Sm),
611 IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", "",
612 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
619 (outs), (ins HPR:$Sd, HPR:$Sm),
620 IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm",
621 [(arm_cmpfp (f16 HPR:$Sd), (f16 HPR:$Sm))]>;
634 (outs SPR:$Sd), (ins SPR:$Sm),
635 IIC_fpUNA32, "vabs", ".f32\t$Sd, $Sm",
636 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
643 (outs HPR:$Sd), (ins HPR:$Sm),
644 IIC_fpUNA16, "vabs", ".f16\t$Sd, $Sm",
645 [(set (f16 HPR:$Sd), (fabs (f16 HPR:$Sm)))]>;
657 (outs), (ins SPR:$Sd),
658 IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", "",
659 [(arm_cmpfpe0 SPR:$Sd)]> {
669 (outs), (ins HPR:$Sd),
670 IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0",
671 [(arm_cmpfpe0 (f16 HPR:$Sd))]> {
685 (outs), (ins SPR:$Sd),
686 IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", "",
687 [(arm_cmpfp0 SPR:$Sd)]> {
697 (outs), (ins HPR:$Sd),
698 IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0",
699 [(arm_cmpfp0 (f16 HPR:$Sd))]> {
725 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
726 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm", "",
727 [(set SPR:$Sd, (fpround DPR:$Dm))]>,
730 bits<5> Sd;
736 let Inst{15-12} = Sd{4-1};
737 let Inst{22} = Sd{0};
751 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
752 /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", "",
763 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
764 /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", "$Sd = $Sda",
785 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
786 /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", "",
799 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
800 /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", "$Sd = $Sda",
840 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm),
841 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm", "$Sd = $Sda",
845 bits<5> Sd;
851 let Inst{15-12} = Sd{4-1};
852 let Inst{22} = Sd{0};
879 (outs SPR:$Sd), (ins SPR:$Sda, DPR:$Dm),
880 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm", "$Sd = $Sda",
883 bits<5> Sd;
887 let Inst{15-12} = Sd{4-1};
888 let Inst{22} = Sd{0};
899 (outs SPR:$Sd), (ins HPR:$Sm),
900 NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"),
907 (outs SPR:$Sd), (ins HPR:$Sm),
908 NoItinerary, !strconcat("vcvt", opc, ".u32.f16\t$Sd, $Sm"),
915 (outs SPR:$Sd), (ins SPR:$Sm),
916 NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
923 (outs SPR:$Sd), (ins SPR:$Sm),
924 NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
931 (outs SPR:$Sd), (ins DPR:$Dm),
932 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
946 (outs SPR:$Sd), (ins DPR:$Dm),
947 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
1005 (outs SPR:$Sd), (ins SPR:$Sm),
1006 IIC_fpUNA32, "vneg", ".f32\t$Sd, $Sm",
1007 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
1014 (outs HPR:$Sd), (ins HPR:$Sm),
1015 IIC_fpUNA16, "vneg", ".f16\t$Sd, $Sm",
1016 [(set (f16 HPR:$Sd), (fneg (f16 HPR:$Sm)))]>;
1020 (outs HPR:$Sd), (ins HPR:$Sm),
1021 NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm",
1022 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>,
1029 (outs SPR:$Sd), (ins SPR:$Sm),
1030 NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm", "",
1031 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
1045 def : InstAlias<!strconcat("vrint", opc, "$p.f16.f16\t$Sd, $Sm"),
1046 (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
1048 def : InstAlias<!strconcat("vrint", opc, "$p.f32.f32\t$Sd, $Sm"),
1049 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
1065 (outs HPR:$Sd), (ins HPR:$Sm),
1066 NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"),
1067 [(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>,
1072 (outs SPR:$Sd), (ins SPR:$Sm),
1073 NoItinerary, !strconcat("vrint", opc, ".f32\t$Sd, $Sm"),
1074 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
1087 def : InstAlias<!strconcat("vrint", opc, ".f16.f16\t$Sd, $Sm"),
1088 (!cast<Instruction>(NAME#"H") HPR:$Sd, HPR:$Sm), 0>,
1090 def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
1091 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>,
1110 (outs SPR:$Sd), (ins SPR:$Sm),
1111 IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm", "",
1112 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>,
1116 (outs HPR:$Sd), (ins HPR:$Sm),
1117 IIC_fpSQRT16, "vsqrt", ".f16\t$Sd, $Sm",
1118 [(set (f16 HPR:$Sd), (fsqrt (f16 HPR:$Sm)))]>;
1128 (outs SPR:$Sd), (ins SPR:$Sm),
1129 IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", "", []>,
1135 (outs SPR:$Sd), (ins SPR:$Sm),
1136 IIC_fpUNA16, "vmovx.f16\t$Sd, $Sm", []>,
1140 (outs SPR:$Sd), (ins SPR:$Sda, SPR:$Sm),
1141 IIC_fpUNA16, "vins.f16\t$Sd, $Sm", []>,
1143 let Constraints = "$Sd = $Sda";
1417 bits<5> Sd;
1423 let Inst{15-12} = Sd{4-1};
1424 let Inst{22} = Sd{0};
1436 bits<5> Sd;
1442 let Inst{15-12} = Sd{4-1};
1443 let Inst{22} = Sd{0};
1466 (outs SPR:$Sd),(ins SPR:$Sm),
1467 IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
1484 (outs HPR:$Sd), (ins SPR:$Sm),
1485 IIC_fpCVTIH, "vcvt", ".f16.s32\t$Sd, $Sm",
1512 (outs SPR:$Sd), (ins SPR:$Sm),
1513 IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
1530 (outs HPR:$Sd), (ins SPR:$Sm),
1531 IIC_fpCVTIH, "vcvt", ".f16.u32\t$Sd, $Sm",
1550 bits<5> Sd;
1556 let Inst{15-12} = Sd{4-1};
1557 let Inst{22} = Sd{0};
1570 bits<5> Sd;
1576 let Inst{15-12} = Sd{4-1};
1577 let Inst{22} = Sd{0};
1589 bits<5> Sd;
1595 let Inst{15-12} = Sd{4-1};
1596 let Inst{22} = Sd{0};
1604 (outs SPR:$Sd), (ins DPR:$Dm),
1605 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
1624 (outs SPR:$Sd), (ins SPR:$Sm),
1625 IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
1648 (outs SPR:$Sd), (ins HPR:$Sm),
1649 IIC_fpCVTHI, "vcvt", ".s32.f16\t$Sd, $Sm",
1662 (outs SPR:$Sd), (ins DPR:$Dm),
1663 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1682 (outs SPR:$Sd), (ins SPR:$Sm),
1683 IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
1706 (outs SPR:$Sd), (ins HPR:$Sm),
1707 IIC_fpCVTHI, "vcvt", ".u32.f16\t$Sd, $Sm",
1722 (outs SPR:$Sd), (ins DPR:$Dm),
1723 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1724 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>,
1730 (outs SPR:$Sd), (ins SPR:$Sm),
1731 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1732 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]>,
1738 (outs SPR:$Sd), (ins SPR:$Sm),
1739 IIC_fpCVTHI, "vcvtr", ".s32.f16\t$Sd, $Sm",
1747 (outs SPR:$Sd), (ins DPR:$Dm),
1748 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1749 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>,
1755 (outs SPR:$Sd), (ins SPR:$Sm),
1756 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1757 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]>,
1763 (outs SPR:$Sd), (ins SPR:$Sm),
1764 IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm",
1774 (outs SPR:$Sd), (ins DPR:$Dm),
1775 IIC_fpCVTDI, "vjcvt", ".s32.f64\t$Sd, $Dm",
1993 : VFPAI<(outs SPR:$Sd), (ins SPR:$dst, SPR:$Sm),
1995 opc, ".bf16.f32\t$Sd, $Sm", "", []>,
1996 RegConstraint<"$dst = $Sd">,
1999 bits<5> Sd;
2005 let Inst{15-12} = Sd{4-1};
2006 let Inst{22} = Sd{0};
2036 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2037 IIC_fpMAC32, "vmla", ".f32\t$Sd, $Sn, $Sm",
2038 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
2040 RegConstraint<"$Sdin = $Sd">,
2049 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2050 IIC_fpMAC16, "vmla", ".f16\t$Sd, $Sn, $Sm",
2051 [(set (f16 HPR:$Sd), (fadd_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)),
2053 RegConstraint<"$Sdin = $Sd">,
2077 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2078 IIC_fpMAC32, "vmls", ".f32\t$Sd, $Sn, $Sm",
2079 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2081 RegConstraint<"$Sdin = $Sd">,
2090 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2091 IIC_fpMAC16, "vmls", ".f16\t$Sd, $Sn, $Sm",
2092 [(set (f16 HPR:$Sd), (fadd_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),
2094 RegConstraint<"$Sdin = $Sd">,
2117 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2118 IIC_fpMAC32, "vnmla", ".f32\t$Sd, $Sn, $Sm",
2119 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2121 RegConstraint<"$Sdin = $Sd">,
2130 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2131 IIC_fpMAC16, "vnmla", ".f16\t$Sd, $Sn, $Sm",
2132 [(set (f16 HPR:$Sd), (fsub_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),
2134 RegConstraint<"$Sdin = $Sd">,
2169 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2170 IIC_fpMAC32, "vnmls", ".f32\t$Sd, $Sn, $Sm",
2171 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
2172 RegConstraint<"$Sdin = $Sd">,
2181 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2182 IIC_fpMAC16, "vnmls", ".f16\t$Sd, $Sn, $Sm",
2183 … [(set (f16 HPR:$Sd), (fsub_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), (f16 HPR:$Sdin)))]>,
2184 RegConstraint<"$Sdin = $Sd">,
2210 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2211 IIC_fpFMAC32, "vfma", ".f32\t$Sd, $Sn, $Sm",
2212 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
2214 RegConstraint<"$Sdin = $Sd">,
2222 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2223 IIC_fpFMAC16, "vfma", ".f16\t$Sd, $Sn, $Sm",
2224 [(set (f16 HPR:$Sd), (fadd_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)),
2226 RegConstraint<"$Sdin = $Sd">,
2262 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2263 IIC_fpFMAC32, "vfms", ".f32\t$Sd, $Sn, $Sm",
2264 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2266 RegConstraint<"$Sdin = $Sd">,
2274 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2275 IIC_fpFMAC16, "vfms", ".f16\t$Sd, $Sn, $Sm",
2276 [(set (f16 HPR:$Sd), (fadd_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),
2278 RegConstraint<"$Sdin = $Sd">,
2314 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2315 IIC_fpFMAC32, "vfnma", ".f32\t$Sd, $Sn, $Sm",
2316 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2318 RegConstraint<"$Sdin = $Sd">,
2326 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2327 IIC_fpFMAC16, "vfnma", ".f16\t$Sd, $Sn, $Sm",
2328 [(set (f16 HPR:$Sd), (fsub_mlx (fneg (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm))),
2330 RegConstraint<"$Sdin = $Sd">,
2373 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2374 IIC_fpFMAC32, "vfnms", ".f32\t$Sd, $Sn, $Sm",
2375 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
2376 RegConstraint<"$Sdin = $Sd">,
2384 (outs HPR:$Sd), (ins HPR:$Sdin, HPR:$Sn, HPR:$Sm),
2385 IIC_fpFMAC16, "vfnms", ".f16\t$Sd, $Sn, $Sm",
2386 … [(set (f16 HPR:$Sd), (fsub_mlx (fmul_su (f16 HPR:$Sn), (f16 HPR:$Sm)), (f16 HPR:$Sdin)))]>,
2387 RegConstraint<"$Sdin = $Sd">,
2432 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
2434 [(set (f32 SPR:$Sd),
2436 RegConstraint<"$Sn = $Sd">, Requires<[HasFPRegs]>;
2438 def VMOVHcc : PseudoInst<(outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm, cmovpred:$p),
2440 [(set (f16 HPR:$Sd),
2442 RegConstraint<"$Sd = $Sn">, Requires<[HasFPRegs]>;
2626 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
2628 "vmov", ".f32\t$Sd, $imm", "",
2629 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
2630 bits<5> Sd;
2634 let Inst{22} = Sd{0};
2637 let Inst{15-12} = Sd{4-1};
2644 def FCONSTH : VFPAI<(outs HPR:$Sd), (ins vfp_f16imm:$imm),
2646 "vmov", ".f16\t$Sd, $imm", "",
2647 [(set (f16 HPR:$Sd), vfp_f16imm:$imm)]>,
2649 bits<5> Sd;
2653 let Inst{22} = Sd{0};
2656 let Inst{15-12} = Sd{4-1};
2723 def : VFP2InstAlias<"fadds${p} $Sd, $Sn, $Sm",
2724 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2727 def : VFP2InstAlias<"fsubs${p} $Sd, $Sn, $Sm",
2728 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2733 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
2737 def : VFP2InstAlias<"vldr${p}.32 $Sd, $addr",
2738 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2739 def : VFP2InstAlias<"vstr${p}.32 $Sd, $addr",
2740 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2767 def : VFP2InstAlias<"vmov${p} $Sd, $Sm",
2768 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
2778 def : VFP3InstAlias<"fconsts${p} $Sd, $val",
2779 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;