Lines Matching refs:Rd
445 bits<4> Rd;
448 let Inst{11-8} = Rd;
458 bits<4> Rd;
462 let Inst{11-8} = Rd;
484 bits<4> Rd;
487 let Inst{11-8} = Rd;
497 bits<4> Rd;
500 let Inst{11-8} = Rd;
523 bits<4> Rd;
526 let Inst{11-8} = Rd;
533 bits<4> Rd;
536 let Inst{11-8} = Rd;
554 bits<4> Rd;
558 let Inst{11-8} = Rd;
568 bits<4> Rd;
572 let Inst{11-8} = Rd;
582 bits<4> Rd;
586 let Inst{11-8} = Rd;
595 bits<4> Rd;
599 let Inst{11-8} = Rd;
608 bits<4> Rd;
612 let Inst{11-8} = Rd;
620 bits<4> Rd;
624 let Inst{11-8} = Rd;
632 bits<4> Rd;
636 let Inst{11-8} = Rd;
644 bits<4> Rd;
648 let Inst{11-8} = Rd;
659 bits<4> Rd;
663 let Inst{11-8} = Rd;
674 bits<4> Rd;
681 let Inst{11-8} = Rd;
733 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
734 opc, "\t$Rd, $Rn, $imm",
735 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
743 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
744 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
745 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
768 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
769 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
770 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
801 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
802 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
805 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
806 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
808 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
809 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
830 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
831 opc, ".w\t$Rd, $Rn, $imm",
832 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,
841 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
842 opc, "\t$Rd, $Rn, $Rm",
854 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
855 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
856 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,
874 def ri : t2PseudoInst<(outs rGPR:$Rd),
877 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
881 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
883 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
889 def rs : t2PseudoInst<(outs rGPR:$Rd),
892 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
903 def ri : t2PseudoInst<(outs rGPR:$Rd),
906 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
910 def rs : t2PseudoInst<(outs rGPR:$Rd),
913 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
928 (outs GPRsp:$Rd), (ins GPRsp:$Rn, t2_so_imm:$imm), IIC_iALUi,
929 opc, ".w\t$Rd, $Rn, $imm",
933 let Rd = 13;
944 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
945 opc, ".w\t$Rd, $Rn, $imm",
946 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
957 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
958 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
959 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
961 bits<4> Rd;
972 let Inst{11-8} = Rd;
976 (outs GPRsp:$Rd), (ins GPRsp:$Rn, imm0_4095:$imm), IIC_iALUi,
977 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
980 bits<4> Rd = 13;
991 let Inst{11-8} = Rd;
996 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
997 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
998 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
1011 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
1012 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
1013 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
1029 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
1030 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1031 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
1039 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
1040 opc, ".w\t$Rd, $Rn, $Rm",
1041 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
1053 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
1054 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
1055 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
1069 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
1070 opc, ".w\t$Rd, $Rm, $imm",
1071 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,
1081 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
1082 opc, ".w\t$Rd, $Rn, $Rm",
1083 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
1101 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
1102 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,
1104 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
1105 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
1134 let Inst{11-8} = 0b1111; // Rd
1146 let Inst{11-8} = 0b1111; // Rd
1160 let Inst{11-8} = 0b1111; // Rd
1346 (outs rGPR:$Rd),
1348 opc, ".w\t$Rd, $Rm$rot", []>,
1355 (outs rGPR:$Rd),
1357 opc, "\t$Rd, $Rm$rot", []>,
1364 : T2ThreeReg<(outs rGPR:$Rd),
1366 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1389 bits<4> Rd;
1392 let Inst{11-8} = Rd;
1400 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1402 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
1412 bits<4> Rd;
1414 let Inst{11-8} = Rd;
1425 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1428 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
2129 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rm), IIC_iMOVr,
2130 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
2139 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
2141 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
2143 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
2149 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
2150 "mov", ".w\t$Rd, $imm",
2151 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
2161 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
2163 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
2166 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
2168 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
2172 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
2173 "movw", "\t$Rd, $imm",
2174 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]>,
2182 bits<4> Rd;
2185 let Inst{11-8} = Rd;
2193 def : InstAlias<"mov${p} $Rd, $imm",
2194 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>,
2199 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
2203 let Constraints = "$src = $Rd" in {
2204 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
2206 "movt", "\t$Rd, $imm",
2207 [(set rGPR:$Rd,
2217 bits<4> Rd;
2220 let Inst{11-8} = Rd;
2230 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
2382 def : t2InstSubst<"subw${p} $Rd, $Rn, $imm",
2383 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
2394 def : t2InstSubst<"subw${p} $Rd, $Rn, $imm",
2395 (t2ADDspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095_neg:$imm, pred:$p)>;
2449 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2450 NoItinerary, "sel", "\t$Rd, $Rn, $Rm",
2451 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,
2466 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
2474 bits<4> Rd;
2478 let Inst{11-8} = Rd;
2486 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm))],
2487 (ins rGPR:$Rn, rGPR:$Rm), "\t$Rd, $Rn, $Rm">;
2491 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2601 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2603 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm",
2604 [(set rGPR:$Rd, (int_arm_usad8 rGPR:$Rn, rGPR:$Rm))]>,
2608 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2610 "usada8", "\t$Rd, $Rn, $Rm, $Ra",
2611 [(set rGPR:$Rd, (int_arm_usada8 rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>,
2616 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, []> {
2617 bits<4> Rd;
2628 let Inst{11-8} = Rd;
2635 "ssat", "\t$Rd, $sat_imm, $Rn$sh">,
2642 "ssat16", "\t$Rd, $sat_imm, $Rn">,
2650 "usat", "\t$Rd, $sat_imm, $Rn$sh">,
2656 "usat16", "\t$Rd, $sat_imm, $Rn">,
2704 def : t2InstAlias<"lsl${s}${p} $Rd, $Rm, #0",
2705 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
2706 def : t2InstAlias<"lsl${s}${p}.w $Rd, $Rm, #0",
2707 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
2714 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2715 "rrx", "\t$Rd, $Rm",
2716 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> {
2730 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2731 "lsrs", ".w\t$Rd, $Rm, #1",
2732 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>,
2745 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2746 "asrs", ".w\t$Rd, $Rm, #1",
2747 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>,
2779 bits<4> Rd;
2783 let Inst{11-8} = Rd;
2797 let Constraints = "$src = $Rd" in
2798 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2799 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2800 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]>, Sched<[WriteALU]> {
2815 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2816 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {
2826 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2827 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {
2850 let Constraints = "$src = $Rd" in {
2851 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2853 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2854 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2872 def : t2InstAlias<"orn${s}${p}.w $Rd, $Rn, $imm",
2873 (t2ORNri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
2874 def : t2InstAlias<"orn${s}${p}.w $Rd, $Rn, $Rm",
2875 (t2ORNrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
2876 def : t2InstAlias<"orn${s}${p}.w $Rd, $Rn, $ShiftedRm",
2877 (t2ORNrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
2887 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2888 opc, "\t$Rd, $imm",
2889 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {
2900 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2901 opc, ".w\t$Rd, $Rm",
2902 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {
2912 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2913 opc, ".w\t$Rd, $ShiftedRm",
2914 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>,
2962 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2963 "mul", "\t$Rd, $Rn, $Rm",
2964 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]>,
2974 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2975 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2985 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm),
2988 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn,
3012 : T2ThreeReg<(outs rGPR:$Rd),
3014 opc, "\t$Rd, $Rn, $Rm", pattern>,
3023 def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,
3027 [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, (i32 0)))]>;
3031 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
3032 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
3042 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;
3044 [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>;
3047 [(set rGPR:$Rd, (ARMsmmlsr rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>;
3051 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, opc,
3052 "\t$Rd, $Rn, $Rm", pattern>,
3064 [(set rGPR:$Rd, (bb_mul rGPR:$Rn, rGPR:$Rm))]>;
3066 [(set rGPR:$Rd, (bt_mul rGPR:$Rn, rGPR:$Rm))]>;
3068 [(set rGPR:$Rd, (tb_mul rGPR:$Rn, rGPR:$Rm))]>;
3070 [(set rGPR:$Rd, (tt_mul rGPR:$Rn, rGPR:$Rm))]>;
3072 [(set rGPR:$Rd, (ARMsmulwb rGPR:$Rn, rGPR:$Rm))]>;
3074 [(set rGPR:$Rd, (ARMsmulwt rGPR:$Rn, rGPR:$Rm))]>;
3098 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16,
3099 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
3110 [(set rGPR:$Rd, (add rGPR:$Ra, (bb_mul rGPR:$Rn, rGPR:$Rm)))]>;
3112 [(set rGPR:$Rd, (add rGPR:$Ra, (bt_mul rGPR:$Rn, rGPR:$Rm)))]>;
3114 [(set rGPR:$Rd, (add rGPR:$Ra, (tb_mul rGPR:$Rn, rGPR:$Rm)))]>;
3116 [(set rGPR:$Rd, (add rGPR:$Ra, (tt_mul rGPR:$Rn, rGPR:$Rm)))]>;
3118 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwb rGPR:$Rn, rGPR:$Rm)))]>;
3120 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwt rGPR:$Rn, rGPR:$Rm)))]>;
3169 (outs rGPR:$Rd),
3171 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm",
3172 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm))]>,
3187 (outs rGPR:$Rd),
3189 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra",
3190 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>,
3200 (outs rGPR:$Ra, rGPR:$Rd),
3202 IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
3203 RegConstraint<"$Ra = $RLo, $Rd = $RHi">,
3225 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
3226 "sdiv", "\t$Rd, $Rn, $Rm",
3227 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
3237 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
3238 "udiv", "\t$Rd, $Rn, $Rm",
3239 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
3265 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3266 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>,
3269 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3270 "rbit", "\t$Rd, $Rm",
3271 [(set rGPR:$Rd, (bitreverse rGPR:$Rm))]>,
3274 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3275 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,
3278 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3279 "rev16", ".w\t$Rd, $Rm",
3280 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>,
3286 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3287 "revsh", ".w\t$Rd, $Rm",
3288 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>,
3296 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
3297 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3298 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
3325 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
3326 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3327 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
3367 : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary,
3368 !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"),
3369 [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>,
3411 let Inst{11-8} = 0b1111; // Rd
3424 let Inst{11-8} = 0b1111; // Rd
3439 let Inst{11-8} = 0b1111; // Rd
3468 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
3471 [(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm,
3473 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3477 : t2PseudoInst<(outs rGPR:$Rd),
3480 [(set rGPR:$Rd, (ARMcmov rGPR:$false,t2_so_imm:$imm,
3482 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3487 : t2PseudoInst<(outs rGPR:$Rd),
3490 [(set rGPR:$Rd, (ARMcmov rGPR:$false, imm0_65535:$imm,
3492 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3496 : t2PseudoInst<(outs rGPR:$Rd),
3499 [(set rGPR:$Rd,
3502 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3505 : t2PseudoInst<(outs rGPR:$Rd),
3508 [(set rGPR:$Rd, (ARMcmov rGPR:$false,
3511 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3600 bits<4> Rd;
3603 let Inst{3-0} = Rd;
3681 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3682 def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd),
3685 "strexb", "\t$Rd, $Rt, $addr", "",
3686 [(set rGPR:$Rd,
3689 def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),
3692 "strexh", "\t$Rd, $Rt, $addr", "",
3693 [(set rGPR:$Rd,
3697 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3700 "strex", "\t$Rd, $Rt, $addr", "",
3701 [(set rGPR:$Rd,
3704 bits<4> Rd;
3711 let Inst{11-8} = Rd;
3715 def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),
3718 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3724 def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),
3727 "stlexb", "\t$Rd, $Rt, $addr", "",
3728 [(set rGPR:$Rd,
3733 def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd),
3736 "stlexh", "\t$Rd, $Rt, $addr", "",
3737 [(set rGPR:$Rd,
3742 def t2STLEX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3745 "stlex", "\t$Rd, $Rt, $addr", "",
3746 [(set rGPR:$Rd,
3750 bits<4> Rd;
3758 let Inst{3-0} = Rd;
3761 def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd),
3764 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
4403 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
4405 bits<4> Rd;
4407 let Inst{11-8} = Rd;
4411 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
4413 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
4415 bits<4> Rd;
4417 let Inst{11-8} = Rd;
4421 def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked),
4422 NoItinerary, "mrs", "\t$Rd, $banked", []>,
4425 bits<4> Rd;
4431 let Inst{11-8} = Rd;
4442 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$SYSm), NoItinerary,
4443 "mrs", "\t$Rd, $SYSm", []>,
4445 bits<4> Rd;
4448 let Inst{11-8} = Rd;
4841 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
4842 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4843 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
4844 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4848 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
4849 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4850 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
4851 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4855 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4856 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p,
4858 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4859 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4860 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
4861 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4862 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
4863 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4879 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
4880 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4882 def : t2InstSubst<"add${p} $Rd, $Rn, $imm",
4883 (t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4890 def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm",
4891 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4893 def : t2InstSubst<"addw${p} $Rd, $Rn, $imm",
4894 (t2SUBri12 rGPR:$Rd, rGPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4903 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4904 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4905 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4906 (t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4907 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
4908 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4909 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
4910 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4929 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4930 (t2ADDspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm:$imm, pred:$p,
4932 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4933 (t2ADDspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095:$imm, pred:$p)>;
4948 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
4949 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm_neg:$imm, pred:$p,
4951 def : t2InstSubst<"add${p} $Rd, $Rn, $imm",
4952 (t2SUBspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4959 def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm",
4960 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm_neg:$imm, pred:$p,
4962 def : t2InstSubst<"addw${p} $Rd, $Rn, $imm",
4963 (t2SUBspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4972 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4973 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4974 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4975 (t2SUBspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095:$imm, pred:$p)>;
5062 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
5063 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
5064 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
5065 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
5066 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
5067 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
5071 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5072 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5074 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5075 (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p), 0>,
5109 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
5110 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
5111 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
5116 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
5117 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
5127 def : t2InstAlias<"rsb${s}${p}.w $Rd, $Rn, $Rm",
5128 (t2RSBrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
5129 def : t2InstAlias<"rsb${s}${p}.w $Rd, $Rn, $ShiftedRm",
5130 (t2RSBrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p,
5134 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5135 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
5136 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5137 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
5160 def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5161 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5163 def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5164 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5166 def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5167 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5169 def : InstAlias<"sxtb16${p} $Rd, $Rm",
5170 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
5173 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
5174 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5175 def : t2InstAlias<"sxth${p} $Rd, $Rm",
5176 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5177 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
5178 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5179 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
5180 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5182 def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5183 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5185 def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5186 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5188 def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5189 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5191 def : InstAlias<"uxtb16${p} $Rd, $Rm",
5192 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
5195 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
5196 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5197 def : t2InstAlias<"uxth${p} $Rd, $Rm",
5198 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5199 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
5200 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5201 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
5202 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5205 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
5206 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
5207 def : InstAlias<"uxtb16${p} $Rd, $Rm$rot",
5208 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
5210 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
5211 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
5213 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
5214 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
5215 def : InstAlias<"sxtb16${p} $Rd, $Rm$rot",
5216 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
5218 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
5219 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
5222 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
5224 def : t2InstSubst<"mov${p} $Rd, $imm",
5225 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
5226 def : t2InstSubst<"mvn${s}${p} $Rd, $imm",
5227 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
5229 def : t2InstSubst<"bic${s}${p} $Rd, $Rn, $imm",
5230 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
5235 def : t2InstSubst<"bic${s}${p}.w $Rd, $Rn, $imm",
5236 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
5241 def : t2InstSubst<"and${s}${p} $Rd, $Rn, $imm",
5242 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
5247 def : t2InstSubst<"and${s}${p}.w $Rd, $Rn, $imm",
5248 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
5254 def : t2InstSubst<"orn${s}${p} $Rd, $Rn, $imm",
5255 (t2ORRri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
5260 def : t2InstSubst<"orr${s}${p} $Rd, $Rn, $imm",
5261 (t2ORNri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
5266 // Likewise, "add Rd, t2_so_imm_neg" -> sub
5267 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
5268 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
5270 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
5271 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm_neg:$imm,
5273 def : t2InstSubst<"add${s}${p} $Rd, $imm",
5274 (t2SUBri rGPR:$Rd, rGPR:$Rd, t2_so_imm_neg:$imm,
5276 def : t2InstSubst<"add${s}${p} $Rd, $imm",
5277 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rd, t2_so_imm_neg:$imm,
5280 def : t2InstSubst<"cmp${p} $Rd, $imm",
5281 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
5282 def : t2InstSubst<"cmn${p} $Rd, $imm",
5283 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
5291 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
5292 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
5298 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
5299 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
5300 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
5301 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
5303 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
5304 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
5305 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
5306 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
5309 def : t2InstAlias<"mov${p}.w $Rd, $shift",
5310 (t2MOVsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
5311 def : t2InstAlias<"movs${p}.w $Rd, $shift",
5312 (t2MOVSsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
5313 def : t2InstAlias<"mov${p}.w $Rd, $shift",
5314 (t2MOVsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
5315 def : t2InstAlias<"movs${p}.w $Rd, $shift",
5316 (t2MOVSsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
5319 def : t2InstAlias<"adr${p} $Rd, $addr",
5320 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
5345 def : t2InstAlias<"add${p} $Rd, pc, $imm",
5346 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;
5597 : V8_1MI<(outs rGPR:$Rd), (ins GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rm, pred_noal:$fcond),
5598 AddrModeNone, NoItinerary, iname, "$Rd, $Rn, $Rm, $fcond", "", pattern> {
5599 bits<4> Rd;
5607 let Inst{11-8} = Rd{3-0};
5660 def : InstAlias<"csetm\t$Rd, $fcond",
5661 (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;
5663 def : InstAlias<"cset\t$Rd, $fcond",
5664 (t2CSINC rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;
5666 def : InstAlias<"cinc\t$Rd, $Rn, $fcond",
5667 (t2CSINC rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;
5669 def : InstAlias<"cinv\t$Rd, $Rn, $fcond",
5670 (t2CSINV rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;
5672 def : InstAlias<"cneg\t$Rd, $Rn, $fcond",
5673 (t2CSNEG rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;
5679 def t2PACG : V8_1MI<(outs rGPR:$Rd),
5681 AddrModeNone, NoItinerary, "pacg${p}", "$Rd, $Rn, $Rm", "", []> {
5682 bits<4> Rd;
5688 let Inst{11-8} = Rd;