Lines Matching refs:IsThumb2
1032 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> {
1042 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> {
1056 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> {
1349 Requires<[IsThumb2]>,
1358 Requires<[HasDSP, IsThumb2]>,
1367 Requires<[HasDSP, IsThumb2]>,
1896 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
1897 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1898 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
1910 Requires<[IsThumb2,HasV7,HasMP]>;
1913 Requires<[IsThumb2,HasV7,HasMP]>;
1916 Requires<[IsThumb2,HasV7,HasMP]>;
1920 Requires<[IsThumb2,HasV7]>;
1923 Requires<[IsThumb2,HasV7]>;
1926 Requires<[IsThumb2,HasV7]>;
1947 def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
1948 def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;
1954 Requires<[IsThumb2,HasV7]>;
1961 Requires<[IsThumb2,HasV7]>;
1966 Requires<[IsThumb2,HasV7]>;
2313 // Requires<[HasDSP, IsThumb2]>;
2316 Requires<[HasDSP, IsThumb2]>;
2452 Requires<[IsThumb2, HasDSP]> {
2467 Requires<[IsThumb2, HasDSP]> {
2605 Requires<[IsThumb2, HasDSP]> {
2612 Requires<[IsThumb2, HasDSP]>;
2636 Requires<[IsThumb2]>, Sched<[WriteALU]> {
2643 Requires<[IsThumb2, HasDSP]>, Sched<[WriteALU]> {
2651 Requires<[IsThumb2]>, Sched<[WriteALU]> {
2657 Requires<[IsThumb2, HasDSP]>, Sched<[WriteALU]> {
2941 Requires<[IsThumb2]>;
2976 Requires<[IsThumb2, UseMulOps]>,
3005 def t2UMAAL : T2MlaLong<0b110, 0b0110, "umaal">, Requires<[IsThumb2, HasDSP]>;
3015 Requires<[IsThumb2, HasDSP]>,
3033 Requires<[IsThumb2, HasDSP, UseMulOps]>,
3053 Requires<[IsThumb2, HasDSP]>,
3100 Requires<[IsThumb2, HasDSP, UseMulOps]>,
3149 Requires<[IsThumb2, HasDSP]>;
3151 Requires<[IsThumb2, HasDSP]>;
3153 Requires<[IsThumb2, HasDSP]>;
3155 Requires<[IsThumb2, HasDSP]>;
3173 Requires<[IsThumb2, HasDSP]>,
3191 Requires<[IsThumb2, HasDSP]>;
3204 Requires<[IsThumb2, HasDSP]>,
3301 Requires<[HasDSP, IsThumb2]>,
3317 Requires<[HasDSP, IsThumb2]>;
3320 Requires<[HasDSP, IsThumb2]>;
3330 Requires<[HasDSP, IsThumb2]>,
3349 Requires<[HasDSP, IsThumb2]>;
3352 Requires<[HasDSP, IsThumb2]>;
3356 Requires<[HasDSP, IsThumb2]>;
3370 Requires<[IsThumb2, HasV8, HasCRC]> {
3570 Requires<[IsThumb2, HasSB]>, Sched<[]> {
3639 Requires<[IsThumb2, IsNotMClass]>, Sched<[WriteLd]> {
3720 Requires<[IsThumb2, IsNotMClass]>, Sched<[WriteST]> {
3831 Requires<[IsThumb2, HasVFP2]>;
3842 Requires<[IsThumb2, NoVFP]>;
3962 Requires<[IsThumb2]>, Sched<[WriteBr]>;
3986 Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass]> {
4031 Requires<[IsThumb2, IsNotMClass]> {
4076 let Predicates = [IsThumb2, HasV8];
4079 let Predicates = [IsThumb2, HasRAS];
4082 let Predicates = [IsThumb2, HasRAS];
4107 []>, Requires<[IsThumb2, HasTrustZone]> {
4117 : T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> {
4133 Requires<[IsThumb2,IsNotMClass]> {
4166 Requires<[IsThumb2,IsNotMClass]> {
4193 Requires<[IsThumb2,IsNotMClass]> {
4210 Requires<[IsThumb2, HasVirtualization]>;
4215 Requires<[IsThumb2, HasVirtualization]>, Sched<[WriteBr]> {
4253 Requires<[IsThumb2, UseMovtInPic]>;
4256 Requires<[IsThumb2, UseMovt]>;
4288 Requires<[IsThumb2]>;
4294 NoItinerary, []>, Requires<[IsThumb2]>;
4385 … 1, 0, "ldc2", [(int_arm_ldc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4386 …, 1, "ldc2l", [(int_arm_ldc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4390 … 0, 0, "stc2", [(int_arm_stc2 timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4391 …, 1, "stc2l", [(int_arm_stc2l timm:$cop, timm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>;
4404 []>, Requires<[IsThumb2,IsNotMClass]> {
4414 []>, Requires<[IsThumb2,IsNotMClass]> {
4467 Requires<[IsThumb2,IsNotMClass]> {
4587 let Predicates = [IsThumb2, PreV8];
4604 let Predicates = [IsThumb2, PreV8];
4628 let Predicates = [IsThumb2, PreV8];
4637 let Predicates = [IsThumb2, PreV8];
4666 let Predicates = [IsThumb2, PreV8];
4692 let Predicates = [IsThumb2, PreV8];
4699 Requires<[IsThumb2, IsReadTPHard]>;
4707 T1Misc<0b0110000>, Requires<[IsThumb2, HasV8, HasV8_1a]> {
4764 Requires<[IsThumb2]>;
4766 Requires<[IsThumb2]>;
4768 Requires<[HasDSP, IsThumb2]>;
4771 Requires<[HasDSP, IsThumb2]>;
4774 Requires<[HasDSP, IsThumb2]>;
4778 Requires<[IsThumb2]>;
4780 Requires<[IsThumb2]>;
4783 Requires<[HasDSP, IsThumb2]>;
4786 Requires<[HasDSP, IsThumb2]>;
5007 def : InstAlias<"ssbb", (t2DSB 0x0, 14, 0), 1>, Requires<[HasDB, IsThumb2]>;
5008 def : InstAlias<"pssbb", (t2DSB 0x4, 14, 0), 1>, Requires<[HasDB, IsThumb2]>;
5073 Requires<[HasDSP, IsThumb2]>;
5076 Requires<[HasDSP, IsThumb2]>;
5162 Requires<[HasDSP, IsThumb2]>;
5165 Requires<[HasDSP, IsThumb2]>;
5168 Requires<[HasDSP, IsThumb2]>;
5171 Requires<[HasDSP, IsThumb2]>;
5184 Requires<[HasDSP, IsThumb2]>;
5187 Requires<[HasDSP, IsThumb2]>;
5190 Requires<[HasDSP, IsThumb2]>;
5193 Requires<[HasDSP, IsThumb2]>;
5209 Requires<[HasDSP, IsThumb2]>;
5217 Requires<[HasDSP, IsThumb2]>;
5386 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB];
5392 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB];
5467 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB];
5518 let Predicates = [IsThumb2, HasV8_1MMainline, HasLOB] in {
5678 let Predicates = [IsThumb2, HasV8_1MMainline, HasPACBTI] in {
5756 Requires<[IsThumb2]>, Sched<[WriteBrL]>;