Lines Matching refs:Rd
399 // ADD <Rd>, sp, #<imm8>
910 bits<3> Rd;
912 let Inst{2-0} = Rd;
920 bits<3> Rd;
923 let Inst{2-0} = Rd;
931 bits<3> Rd;
934 let Inst{2-0} = Rd;
940 bits<3> Rd;
943 let Inst{2-0} = Rd;
976 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
978 "add", "\t$Rd, $Rm, $imm3",
979 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
995 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
997 "add", "\t$Rd, $Rn, $Rm",
998 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1014 def tADDSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1016 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rm,
1029 def tADDSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1031 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rn,
1078 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1080 "asr", "\t$Rd, $Rm, $imm5",
1081 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1163 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
1165 "lsl", "\t$Rd, $Rm, $imm5",
1166 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
1181 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1183 "lsr", "\t$Rd, $Rm, $imm5",
1184 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1199 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1200 "mov", "\t$Rd, $imm8",
1201 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1204 bits<3> Rd;
1206 let Inst{10-8} = Rd;
1217 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1219 "mov", "\t$Rd, $Rm", "", []>,
1222 bits<4> Rd;
1224 let Inst{7} = Rd{3};
1226 let Inst{2-0} = Rd{2-0};
1229 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1230 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
1232 bits<3> Rd;
1236 let Inst{2-0} = Rd;
1243 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1244 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1245 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1247 bits<3> Rd;
1250 let Inst{2-0} = Rd;
1259 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1260 "mvn", "\t$Rd, $Rn",
1261 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
1273 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1275 "rev", "\t$Rd, $Rm",
1276 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1280 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1282 "rev16", "\t$Rd, $Rm",
1283 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1287 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1289 "revsh", "\t$Rd, $Rm",
1290 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1303 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1305 "rsb", "\t$Rd, $Rn, #0",
1306 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
1319 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1321 "sub", "\t$Rd, $Rm, $imm3",
1322 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1345 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1347 "sub", "\t$Rd, $Rn, $Rm",
1348 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
1368 def tSUBSi3 : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1370 [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rm,
1382 def tSUBSrr : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1384 [(set tGPR:$Rd, CPSR, (ARMsubc tGPR:$Rn,
1389 def tRSBS : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn),
1391 [(set tGPR:$Rd, CPSR, (ARMsubc 0, tGPR:$Rn))]>,
1395 def tLSLSri : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn, imm0_31:$imm5),
1397 [(set tGPR:$Rd, CPSR, (ARMlsls tGPR:$Rn, imm0_31:$imm5))]>,
1410 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1412 "sxtb", "\t$Rd, $Rm",
1413 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1419 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1421 "sxth", "\t$Rd, $Rm",
1422 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1455 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1457 "uxtb", "\t$Rd, $Rm",
1458 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1464 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1466 "uxth", "\t$Rd, $Rm",
1467 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1481 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1482 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1484 bits<3> Rd;
1486 let Inst{10-8} = Rd;
1492 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1496 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1759 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1760 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
1783 let Constraints = "@earlyclobber $Rd,@earlyclobber $temp",
1785 def tCMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, tGPR:$temp),
1789 def tCMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, tGPR:$temp),
1793 def tCMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, tGPR:$temp),