Lines Matching refs:QPR
558 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
560 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
564 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
568 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1004 : PseudoNLdSt<(outs QPR:$dst),
1005 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1008 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1009 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1055 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1080 def : Pat<(vector_insert (v8f16 QPR:$src),
1082 (VLD1LNq16Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1086 def : Pat<(vector_insert (v8bf16 QPR:$src),
1088 (VLD1LNq16Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1092 def : Pat<(vector_insert (v4f32 QPR:$src),
1094 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1666 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1669 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1673 (ins addrmode6:$addr, QPR:$src), itin,
1677 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
2128 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
2132 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
2162 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2189 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
2190 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
2194 def : Pat<(store (extractelt (v8f16 QPR:$src), imm:$lane), addrmode6:$addr),
2195 (VST1LNq16Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
2213 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2484 def : Pat<(dword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2485 (VST1q64 addrmode6:$addr, QPR:$value)>;
2490 def : Pat<(word_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2491 (VST1q32 addrmode6:$addr, QPR:$value)>;
2494 def : Pat<(hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2495 (VST1q16 addrmode6:$addr, QPR:$value)>;
2498 def : Pat<(byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2499 (VST1q8 addrmode6:$addr, QPR:$value)>;
2516 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2517 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2518 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2532 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2533 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2534 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2547 : N2Vnp<op19_18, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2549 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2555 : N2Vnp<op19_18, op17_16, op10_8, op7, op6, (outs QPR:$Vd), (ins QPR:$Vm),
2557 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2564 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
2566 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
2576 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2577 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2585 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2586 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2593 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2595 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2602 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2604 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2614 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2615 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2674 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2676 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2685 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2687 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2696 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2698 [(set (ResTy QPR:$Vd),
2699 (ResTy (ShOp (ResTy QPR:$Vn),
2709 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2711 [(set (ResTy QPR:$Vd),
2712 (ResTy (ShOp (ResTy QPR:$Vn),
2781 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2783 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2794 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
2795 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2805 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm),
2807 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
2808 (OpTy QPR:$Vm))))]> {
2817 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2819 [(set (ResTy QPR:$Vd),
2820 (ResTy (IntOp (ResTy QPR:$Vn),
2829 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2831 [(set (ResTy QPR:$Vd),
2832 (ResTy (IntOp (ResTy QPR:$Vn),
2841 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2843 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2889 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2891 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2892 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2897 (outs QPR:$Vd),
2898 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2901 [(set (ResTy QPR:$Vd),
2902 (ResTy (ShOp (ResTy QPR:$src1),
2903 (ResTy (MulOp QPR:$Vn,
2911 (outs QPR:$Vd),
2912 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2915 [(set (ResTy QPR:$Vd),
2916 (ResTy (ShOp (ResTy QPR:$src1),
2917 (ResTy (MulOp QPR:$Vn,
2934 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2936 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2937 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2953 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2955 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2956 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2963 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2965 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2971 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2972 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2975 [(set QPR:$Vd,
2976 (OpNode (TyQ QPR:$src1),
2983 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2984 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2987 [(set QPR:$Vd,
2988 (OpNode (TyQ QPR:$src1),
2999 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3001 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
3011 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3013 [(set QPR:$Vd,
3014 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
3019 (outs QPR:$Vd),
3020 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3023 [(set (ResTy QPR:$Vd),
3024 (ResTy (IntOp (ResTy QPR:$src1),
3032 (outs QPR:$Vd),
3033 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3036 [(set (ResTy QPR:$Vd),
3037 (ResTy (IntOp (ResTy QPR:$src1),
3047 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
3049 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
3058 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3060 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
3068 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3070 [(set QPR:$Vd,
3077 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3079 [(set QPR:$Vd,
3089 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3091 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3102 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3104 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3114 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3116 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
3126 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
3127 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
3136 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3138 [(set (ResTy QPR:$Vd),
3146 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3148 [(set (ResTy QPR:$Vd),
3158 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
3160 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
3179 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
3180 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3181 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
3199 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
3201 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
3217 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3219 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
3228 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3230 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
3238 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3240 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3257 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3258 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3260 [(set QPR:$Vd, (Ty (add QPR:$src1,
3261 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
3277 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3278 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
3280 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3296 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3298 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
3346 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3348 [(set QPR:$Vd, (v16i8 (ARMvcmpz (v16i8 QPR:$Vm), fc)))]>;
3350 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3352 [(set QPR:$Vd, (v8i16 (ARMvcmpz (v8i16 QPR:$Vm), fc)))]>;
3354 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3356 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4i32 QPR:$Vm), fc)))]>;
3358 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3360 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4f32 QPR:$Vm), fc)))]> {
3364 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3366 [(set QPR:$Vd, (v8i16 (ARMvcmpz (v8f16 QPR:$Vm), fc)))]>,
3377 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
3379 [(set QPR:$Vd, (ResTy (ARMvcmp (OpTy QPR:$Vn), (OpTy QPR:$Vm), fc)))]> {
4300 def : Pat<(v8i8 (trunc (ARMvshruImm (add (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4301 (VADDHNv8i8 QPR:$Vn, QPR:$Vm)>;
4302 def : Pat<(v4i16 (trunc (ARMvshruImm (add (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4303 (VADDHNv4i16 QPR:$Vn, QPR:$Vm)>;
4304 def : Pat<(v2i32 (trunc (ARMvshruImm (add (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4305 (VADDHNv2i32 QPR:$Vn, QPR:$Vm)>;
4338 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
4339 (v8i16 (ARMvduplane (v8i16 QPR:$src2), imm:$lane)))),
4340 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
4341 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4344 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
4345 (v4i32 (ARMvduplane (v4i32 QPR:$src2), imm:$lane)))),
4346 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
4347 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4350 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
4351 (v4f32 (ARMvduplane (v4f32 QPR:$src2), imm:$lane)))),
4352 (v4f32 (VMULslfq (v4f32 QPR:$src1),
4353 (v2f32 (EXTRACT_SUBREG QPR:$src2,
4356 def : Pat<(v8f16 (fmul (v8f16 QPR:$src1),
4357 (v8f16 (ARMvduplane (v8f16 QPR:$src2), imm:$lane)))),
4358 (v8f16 (VMULslhq(v8f16 QPR:$src1),
4359 (v4f16 (EXTRACT_SUBREG QPR:$src2,
4371 def : Pat<(v4f32 (fmul QPR:$Rn, (ARMvdup (f32 SPR:$Rm)))),
4372 (VMULslfq QPR:$Rn,
4375 def : Pat<(v8f16 (fmul QPR:$Rn, (ARMvdup (f16 HPR:$Rm)))),
4376 (VMULslhq QPR:$Rn,
4390 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
4391 (v8i16 (ARMvduplane (v8i16 QPR:$src2),
4393 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
4394 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4397 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
4398 (v4i32 (ARMvduplane (v4i32 QPR:$src2),
4400 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
4401 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4415 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
4416 (v8i16 (ARMvduplane (v8i16 QPR:$src2),
4418 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
4419 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4422 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
4423 (v4i32 (ARMvduplane (v4i32 QPR:$src2),
4425 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
4426 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4486 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4487 (mul (v8i16 QPR:$src2),
4488 (v8i16 (ARMvduplane (v8i16 QPR:$src3), imm:$lane))))),
4489 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4490 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4494 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
4495 (mul (v4i32 QPR:$src2),
4496 (v4i32 (ARMvduplane (v4i32 QPR:$src3), imm:$lane))))),
4497 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4498 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4503 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
4504 (fmul_su (v4f32 QPR:$src2),
4505 (v4f32 (ARMvduplane (v4f32 QPR:$src3), imm:$lane))))),
4506 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
4507 (v4f32 QPR:$src2),
4508 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4535 def : Pat<(v8i16 (int_arm_neon_vqrdmlah (v8i16 QPR:$src1), (v8i16 QPR:$Vn),
4536 (v8i16 QPR:$Vm))),
4537 (v8i16 (VQRDMLAHv8i16 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4538 def : Pat<(v4i32 (int_arm_neon_vqrdmlah (v4i32 QPR:$src1), (v4i32 QPR:$Vn),
4539 (v4i32 QPR:$Vm))),
4540 (v4i32 (VQRDMLAHv4i32 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4557 def : Pat<(v8i16 (int_arm_neon_vqrdmlah (v8i16 QPR:$src1),
4558 (v8i16 QPR:$src2),
4559 (v8i16 (ARMvduplane (v8i16 QPR:$src3),
4561 (v8i16 (VQRDMLAHslv8i16 (v8i16 QPR:$src1),
4562 (v8i16 QPR:$src2),
4564 QPR:$src3,
4567 def : Pat<(v4i32 (int_arm_neon_vqrdmlah (v4i32 QPR:$src1),
4568 (v4i32 QPR:$src2),
4569 (v4i32 (ARMvduplane (v4i32 QPR:$src3),
4571 (v4i32 (VQRDMLAHslv4i32 (v4i32 QPR:$src1),
4572 (v4i32 QPR:$src2),
4574 QPR:$src3,
4589 def : Pat<(v8i16 (int_arm_neon_vqrdmlsh (v8i16 QPR:$src1), (v8i16 QPR:$Vn),
4590 (v8i16 QPR:$Vm))),
4591 (v8i16 (VQRDMLSHv8i16 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4592 def : Pat<(v4i32 (int_arm_neon_vqrdmlsh (v4i32 QPR:$src1), (v4i32 QPR:$Vn),
4593 (v4i32 QPR:$Vm))),
4594 (v4i32 (VQRDMLSHv4i32 QPR:$src1, QPR:$Vn, QPR:$Vm))>;
4610 def : Pat<(v8i16 (int_arm_neon_vqrdmlsh (v8i16 QPR:$src1),
4611 (v8i16 QPR:$src2),
4612 (v8i16 (ARMvduplane (v8i16 QPR:$src3),
4614 (v8i16 (VQRDMLSHslv8i16 (v8i16 QPR:$src1),
4615 (v8i16 QPR:$src2),
4617 QPR:$src3,
4620 def : Pat<(v4i32 (int_arm_neon_vqrdmlsh (v4i32 QPR:$src1),
4621 (v4i32 QPR:$src2),
4622 (v4i32 (ARMvduplane (v4i32 QPR:$src3),
4624 (v4i32 (VQRDMLSHslv4i32 (v4i32 QPR:$src1),
4625 (v4i32 QPR:$src2),
4627 QPR:$src3,
4637 def : Pat<(v4i32 (saddsat (v4i32 QPR:$src1),
4640 (VQDMLALv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4641 def : Pat<(v2i64 (saddsat (v2i64 QPR:$src1),
4644 (VQDMLALv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4645 def : Pat<(v4i32 (saddsat (v4i32 QPR:$src1),
4649 (VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4650 def : Pat<(v2i64 (saddsat (v2i64 QPR:$src1),
4654 (VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4688 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4689 (mul (v8i16 QPR:$src2),
4690 (v8i16 (ARMvduplane (v8i16 QPR:$src3), imm:$lane))))),
4691 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4692 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4696 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
4697 (mul (v4i32 QPR:$src2),
4698 (v4i32 (ARMvduplane (v4i32 QPR:$src3), imm:$lane))))),
4699 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4700 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4705 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
4706 (fmul_su (v4f32 QPR:$src2),
4707 (v4f32 (ARMvduplane (v4f32 QPR:$src3), imm:$lane))))),
4708 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
4709 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4729 def : Pat<(v4i32 (ssubsat (v4i32 QPR:$src1),
4732 (VQDMLSLv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4733 def : Pat<(v2i64 (ssubsat (v2i64 QPR:$src1),
4736 (VQDMLSLv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4737 def : Pat<(v4i32 (ssubsat (v4i32 QPR:$src1),
4741 (VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4742 def : Pat<(v2i64 (ssubsat (v2i64 QPR:$src1),
4746 (VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4783 def : Pat<(v8f16 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)),
4784 (VFMAhq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4789 def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)),
4790 (VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4795 def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)),
4796 (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4820 def VUDOTQ : VDOT<1, 1, 0, QPR, "vudot", "u8", v4i32, v16i8, int_arm_neon_udot>;
4821 def VSDOTQ : VDOT<1, 0, 0, QPR, "vsdot", "s8", v4i32, v16i8, int_arm_neon_sdot>;
4851 defm VUDOTQI : DOTI<"vudot", "u8", 0b1, 0b1, QPR, v4i32, v16i8,
4852 int_arm_neon_udot, (EXTRACT_SUBREG QPR:$Vm, dsub_0)>;
4853 defm VSDOTQI : DOTI<"vsdot", "s8", 0b1, 0b0, QPR, v4i32, v16i8,
4854 int_arm_neon_sdot, (EXTRACT_SUBREG QPR:$Vm, dsub_0)>;
4860 : N3Vnp<{0b1100, B}, 0b10, 0b1100, 1, U, (outs QPR:$dst),
4861 (ins QPR:$Vd, QPR:$Vn, QPR:$Vm), N3RegFrm, NoItinerary,
4863 [(set (v4i32 QPR:$dst), (OpNode (v4i32 QPR:$Vd),
4864 (v16i8 QPR:$Vn),
4865 (v16i8 QPR:$Vm)))]> {
4909 def VUSDOTQ : VDOT<1, 0, 1, QPR, "vusdot", "s8", v4i32, v16i8, int_arm_neon_usdot>;
4913 defm VUSDOTQI : N3VMixedDotLane<1, 0, "vusdot", "s8", QPR, v4i32, v16i8,
4914 int_arm_neon_usdot, (EXTRACT_SUBREG QPR:$Vm, dsub_0)>;
4916 defm VSUDOTQI : SUDOTLane<1, QPR, v4i32, v16i8, (EXTRACT_SUBREG QPR:$Vm, dsub_0)>;
4972 def v8f16 : BaseN3VCP8ComplexTied<op21, op4, 0, 1, IIC_VMACQ, (outs QPR:$Vd),
4973 (ins QPR:$src1, QPR:$Vn, QPR:$Vm, complexrotateop:$rot),
4980 def v4f32 : BaseN3VCP8ComplexTied<op21, op4, 1, 1, IIC_VMACQ, (outs QPR:$Vd),
4981 (ins QPR:$src1, QPR:$Vn, QPR:$Vm, complexrotateop:$rot),
4994 (outs QPR:$Vd),
4995 (ins QPR:$Vn, QPR:$Vm, complexrotateopodd:$rot),
5004 (outs QPR:$Vd),
5005 (ins QPR:$Vn, QPR:$Vm, complexrotateopodd:$rot),
5020 (outs QPR:$Vd),
5021 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm,
5032 (outs QPR:$Vd),
5033 (ins QPR:$src1, QPR:$Vn, DPR:$Vm, VectorIndex64:$lane,
5048 def : Pat<(v8f16 (int_arm_neon_vcadd_rot90 (v8f16 QPR:$Rn), (v8f16 QPR:$Rm))),
5049 (VCADDv8f16 (v8f16 QPR:$Rn), (v8f16 QPR:$Rm), (i32 0))>;
5050 def : Pat<(v8f16 (int_arm_neon_vcadd_rot270 (v8f16 QPR:$Rn), (v8f16 QPR:$Rm))),
5051 (VCADDv8f16 (v8f16 QPR:$Rn), (v8f16 QPR:$Rm), (i32 1))>;
5058 def : Pat<(v4f32 (int_arm_neon_vcadd_rot90 (v4f32 QPR:$Rn), (v4f32 QPR:$Rm))),
5059 (VCADDv4f32 (v4f32 QPR:$Rn), (v4f32 QPR:$Rm), (i32 0))>;
5060 def : Pat<(v4f32 (int_arm_neon_vcadd_rot270 (v4f32 QPR:$Rn), (v4f32 QPR:$Rm))),
5061 (VCADDv4f32 (v4f32 QPR:$Rn), (v4f32 QPR:$Rm), (i32 1))>;
5108 def : Pat<(v8i8 (trunc (ARMvshruImm (sub (v8i16 QPR:$Vn), QPR:$Vm), 8))),
5109 (VSUBHNv8i8 QPR:$Vn, QPR:$Vm)>;
5110 def : Pat<(v4i16 (trunc (ARMvshruImm (sub (v4i32 QPR:$Vn), QPR:$Vm), 16))),
5111 (VSUBHNv4i16 QPR:$Vn, QPR:$Vm)>;
5112 def : Pat<(v2i32 (trunc (ARMvshruImm (sub (v2i64 QPR:$Vn), QPR:$Vm), 32))),
5113 (VSUBHNv2i32 QPR:$Vn, QPR:$Vm)>;
5211 (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5215 (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5220 (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5224 (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5255 : N3VLaneCP8<0, S, 1, 1, (outs QPR:$Vd),
5266 def VFMALQ : N3VCP8F16Q1<"vfmal", QPR, DPR, DPR, 0b00, 0b10, 1>;
5267 def VFMSLQ : N3VCP8F16Q1<"vfmsl", QPR, DPR, DPR, 0b01, 0b10, 1>;
5278 (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5282 (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5287 (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5291 (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5329 def : Pat<(v16i8 (OpNodeQ QPR:$LHS, QPR:$RHS)),
5330 (!cast<Instruction>(Name#"q") QPR:$LHS, QPR:$RHS)>;
5331 def : Pat<(v8i16 (OpNodeQ QPR:$LHS, QPR:$RHS)),
5332 (!cast<Instruction>(Name#"q") QPR:$LHS, QPR:$RHS)>;
5333 def : Pat<(v2i64 (OpNodeQ QPR:$LHS, QPR:$RHS)),
5334 (!cast<Instruction>(Name#"q") QPR:$LHS, QPR:$RHS)>;
5362 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
5365 [(set QPR:$Vd,
5366 (v8i16 (ARMvorrImm QPR:$src, timm:$SIMM)))]> {
5371 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
5374 [(set QPR:$Vd,
5375 (v4i32 (ARMvorrImm QPR:$src, timm:$SIMM)))]> {
5387 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5388 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
5390 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
5391 (vnotq QPR:$Vm))))]>;
5418 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
5421 [(set QPR:$Vd,
5422 (v8i16 (ARMvbicImm QPR:$src, timm:$SIMM)))]> {
5427 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
5430 [(set QPR:$Vd,
5431 (v4i32 (ARMvbicImm QPR:$src, timm:$SIMM)))]> {
5441 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
5442 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
5444 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
5445 (vnotq QPR:$Vm))))]>;
5463 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
5466 [(set QPR:$Vd, (v8i16 (ARMvmvnImm timm:$SIMM)))]> {
5477 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
5480 [(set QPR:$Vd, (v4i32 (ARMvmvnImm timm:$SIMM)))]> {
5491 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
5493 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
5501 def : Pat<(v2i64 (vnotq QPR:$src)),
5502 (VMVNq QPR:$src)>;
5503 def : Pat<(v8i16 (vnotq QPR:$src)),
5504 (VMVNq QPR:$src)>;
5505 def : Pat<(v16i8 (vnotq QPR:$src)),
5506 (VMVNq QPR:$src)>;
5550 : PseudoNeonI<(outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5552 [(set QPR:$Vd,
5553 (v4i32 (NEONvbsp QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
5555 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 QPR:$src1),
5556 (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))),
5557 (VBSPq QPR:$src1, QPR:$Vn, QPR:$Vm)>;
5558 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 QPR:$src1),
5559 (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))),
5560 (VBSPq QPR:$src1, QPR:$Vn, QPR:$Vm)>;
5561 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1),
5562 (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))),
5563 (VBSPq QPR:$src1, QPR:$Vn, QPR:$Vm)>;
5564 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 QPR:$src1),
5565 (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))),
5566 (VBSPq QPR:$src1, QPR:$Vn, QPR:$Vm)>;
5567 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 QPR:$src1),
5568 (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))),
5569 (VBSPq QPR:$src1, QPR:$Vn, QPR:$Vm)>;
5571 def : Pat<(v16i8 (or (and QPR:$Vn, QPR:$Vd),
5572 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5573 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
5574 def : Pat<(v8i16 (or (and QPR:$Vn, QPR:$Vd),
5575 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5576 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
5577 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
5578 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5579 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
5580 def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
5581 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5582 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
5592 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5593 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5606 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5619 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5938 def : Pat<(v16i8 (ARMvshls (v16i8 QPR:$Dn), (v16i8 QPR:$Dm))),
5939 (VSHLsv16i8 QPR:$Dn, QPR:$Dm)>;
5940 def : Pat<(v8i16 (ARMvshls (v8i16 QPR:$Dn), (v8i16 QPR:$Dm))),
5941 (VSHLsv8i16 QPR:$Dn, QPR:$Dm)>;
5942 def : Pat<(v4i32 (ARMvshls (v4i32 QPR:$Dn), (v4i32 QPR:$Dm))),
5943 (VSHLsv4i32 QPR:$Dn, QPR:$Dm)>;
5944 def : Pat<(v2i64 (ARMvshls (v2i64 QPR:$Dn), (v2i64 QPR:$Dm))),
5945 (VSHLsv2i64 QPR:$Dn, QPR:$Dm)>;
5955 def : Pat<(v16i8 (ARMvshlu (v16i8 QPR:$Dn), (v16i8 QPR:$Dm))),
5956 (VSHLuv16i8 QPR:$Dn, QPR:$Dm)>;
5957 def : Pat<(v8i16 (ARMvshlu (v8i16 QPR:$Dn), (v8i16 QPR:$Dm))),
5958 (VSHLuv8i16 QPR:$Dn, QPR:$Dm)>;
5959 def : Pat<(v4i32 (ARMvshlu (v4i32 QPR:$Dn), (v4i32 QPR:$Dm))),
5960 (VSHLuv4i32 QPR:$Dn, QPR:$Dm)>;
5961 def : Pat<(v2i64 (ARMvshlu (v2i64 QPR:$Dn), (v2i64 QPR:$Dm))),
5962 (VSHLuv2i64 QPR:$Dn, QPR:$Dm)>;
6024 def : Pat<(v8i8 (trunc (ARMvshruImm (v8i16 QPR:$Vn), shr_imm8:$amt))),
6025 (VSHRNv8i8 QPR:$Vn, shr_imm8:$amt)>;
6026 def : Pat<(v4i16 (trunc (ARMvshruImm (v4i32 QPR:$Vn), shr_imm16:$amt))),
6027 (VSHRNv4i16 QPR:$Vn, shr_imm16:$amt)>;
6028 def : Pat<(v2i32 (trunc (ARMvshruImm (v2i64 QPR:$Vn), shr_imm32:$amt))),
6029 (VSHRNv2i32 QPR:$Vn, shr_imm32:$amt)>;
6141 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
6143 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
6159 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
6161 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
6168 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
6170 [(set QPR:$Vd, (v8f16 (fneg QPR:$Vm)))]>,
6177 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
6178 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
6179 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
6211 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
6221 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
6233 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
6236 [(set QPR:$Vd, (v16i8 (ARMvmovImm timm:$SIMM)))]>;
6245 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
6248 [(set QPR:$Vd, (v8i16 (ARMvmovImm timm:$SIMM)))]> {
6259 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
6262 [(set QPR:$Vd, (v4i32 (ARMvmovImm timm:$SIMM)))]> {
6270 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
6273 [(set QPR:$Vd, (v2i64 (ARMvmovImm timm:$SIMM)))]>;
6279 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
6282 [(set QPR:$Vd, (v4f32 (ARMvmovFPImm timm:$SIMM)))]>;
6297 (VMOVv16i8 QPR:$Vd, nImmVMOVIReplicate<i8, To>:$Vm, pred:$p)>;
6305 (VMOVv16i8 QPR:$Vd, nImmVINVIReplicate<i8, To>:$Vm, pred:$p)>;
6321 (V16 QPR:$Vd, nImmVMOVIReplicate<From, To>:$Vm, pred:$p)>;
6325 (NV16 QPR:$Vd, nImmVMOVIReplicate<From, To>:$Vm, pred:$p)>;
6351 def VMOVQ0 : ARMPseudoExpand<(outs QPR:$Vd), (ins), 4, IIC_VMOVImm,
6352 [(set QPR:$Vd, (v4i32 ARMimmAllZerosV))],
6353 (VMOVv4i32 QPR:$Vd, 0, (ops 14, zero_reg))>,
6401 def : Pat<(ARMvgetlanes (v16i8 QPR:$src), imm:$lane),
6402 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
6405 def : Pat<(ARMvgetlanes (v8i16 QPR:$src), imm:$lane),
6406 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
6409 def : Pat<(ARMvgetlaneu (v16i8 QPR:$src), imm:$lane),
6410 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
6413 def : Pat<(ARMvgetlaneu (v8i16 QPR:$src), imm:$lane),
6414 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
6417 def : Pat<(ARMvgetlaneu (v8f16 QPR:$src), imm:$lane),
6418 (VGETLNu16 (v4f16 (EXTRACT_SUBREG QPR:$src,
6423 def : Pat<(ARMvgetlaneu (v8bf16 QPR:$src), imm:$lane),
6424 (VGETLNu16 (v4bf16 (EXTRACT_SUBREG QPR:$src,
6430 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
6431 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
6439 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
6441 (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
6447 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
6448 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
6450 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
6451 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
6452 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
6453 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
6461 def : Pat<(extractelt (VT8 QPR:$src), imm_even:$lane),
6463 (v4f32 (COPY_TO_REGCLASS (VT8 QPR:$src), QPR_VFP2)),
6474 def : Pat<(extractelt (VT8 QPR:$src), imm_odd:$lane),
6477 (v4f32 (COPY_TO_REGCLASS (VT8 QPR:$src), QPR_VFP2)),
6502 def : Pat<(extractelt (v8bf16 QPR:$src), imm_odd:$lane),
6504 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
6548 def : Pat<(insertelt (VT8 QPR:$src1), (VTScalar HPR:$src2), imm:$lane),
6549 (VT8 (INSERT_SUBREG QPR:$src1,
6550 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
6558 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
6559 (v16i8 (INSERT_SUBREG QPR:$src1,
6560 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
6564 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
6565 (v8i16 (INSERT_SUBREG QPR:$src1,
6566 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
6570 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
6571 (v4i32 (INSERT_SUBREG QPR:$src1,
6572 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
6580 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
6581 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
6586 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
6587 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
6632 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
6634 [(set QPR:$V, (Ty (ARMvdup (i32 GPR:$R))))]>;
6666 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6668 [(set QPR:$Vd, (ResTy (ARMvduplane (OpTy DPR:$Vm),
6708 def : Pat<(v16i8 (ARMvduplane (v16i8 QPR:$src), imm:$lane)),
6709 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
6712 def : Pat<(v8i16 (ARMvduplane (v8i16 QPR:$src), imm:$lane)),
6713 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
6716 def : Pat<(v8f16 (ARMvduplane (v8f16 QPR:$src), imm:$lane)),
6717 (v8f16 (VDUPLN16q (v4f16 (EXTRACT_SUBREG QPR:$src,
6720 def : Pat<(v4i32 (ARMvduplane (v4i32 QPR:$src), imm:$lane)),
6721 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
6724 def : Pat<(v4f32 (ARMvduplane (v4f32 QPR:$src), imm:$lane)),
6725 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
6747 def : Pat<(v8bf16 (ARMvduplane (v8bf16 QPR:$src), imm:$lane)),
6748 (v8bf16 (VDUPLN16q (v4bf16 (EXTRACT_SUBREG QPR:$src,
6912 (VCVTf2sq QPR:$Qd, QPR:$Qm, pred:$p)>;
6914 (VCVTf2uq QPR:$Qd, QPR:$Qm, pred:$p)>;
6916 (VCVTs2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
6918 (VCVTu2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
6930 (VCVTh2sq QPR:$Qd, QPR:$Qm, pred:$p)>;
6932 (VCVTh2uq QPR:$Qd, QPR:$Qm, pred:$p)>;
6934 (VCVTs2hq QPR:$Qd, QPR:$Qm, pred:$p)>;
6936 (VCVTu2hq QPR:$Qd, QPR:$Qm, pred:$p)>;
6949 def : Pat<(v4f16 (fpround (v4f32 QPR:$src))), (VCVTf2h QPR:$src)>;
6962 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
6963 (ins QPR:$Vm), IIC_VMOVQ,
6965 [(set QPR:$Vd, (Ty (ARMvrev64 (Ty QPR:$Vm))))]>;
6979 def : Pat<(v4f32 (ARMvrev64 (v4f32 QPR:$Vm))),
6980 (VREV64q32 QPR:$Vm)>;
6981 def : Pat<(v8f16 (ARMvrev64 (v8f16 QPR:$Vm))),
6982 (VREV64q16 QPR:$Vm)>;
6995 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
6996 (ins QPR:$Vm), IIC_VMOVQ,
6998 [(set QPR:$Vd, (Ty (ARMvrev32 (Ty QPR:$Vm))))]>;
7007 def : Pat<(v8f16 (ARMvrev32 (v8f16 QPR:$Vm))),
7008 (VREV32q16 QPR:$Vm)>;
7021 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
7022 (ins QPR:$Vm), IIC_VMOVQ,
7024 [(set QPR:$Vd, (Ty (ARMvrev16 (Ty QPR:$Vm))))]>;
7034 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
7035 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>,
7067 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
7068 (ins QPR:$Vn, QPR:$Vm, immTy:$index), NVExtFrm,
7070 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
7071 (Ty QPR:$Vm), imm:$index)))]> {
7106 def : Pat<(v8f16 (NEONvext (v8f16 QPR:$Vn), (v8f16 QPR:$Vm), (i32 imm:$index))),
7107 (VEXTq16 QPR:$Vn, QPR:$Vm, imm:$index)>;
7119 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn), (v4f32 QPR:$Vm), (i32 imm:$index))),
7120 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
7296 (!cast<Instruction>(NAME#"Qf") QPR:$Qd, QPR:$Qm)>;
7301 (!cast<Instruction>(NAME#"Qh") QPR:$Qd, QPR:$Qm)>;
7473 def : VFPPat<(f64 (sint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
7474 (VSITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
7477 def : VFPPat<(f64 (uint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
7478 (VUITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
7509 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
7510 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
7512 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
7513 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
7515 def : Pat<(v8i16 (bitconvert (v8f16 QPR:$src))), (v8i16 QPR:$src)>;
7516 def : Pat<(v8f16 (bitconvert (v8i16 QPR:$src))), (v8f16 QPR:$src)>;
7518 def : Pat<(v8i16 (bitconvert (v8bf16 QPR:$src))), (v8i16 QPR:$src)>;
7519 def : Pat<(v8bf16 (bitconvert (v8i16 QPR:$src))), (v8bf16 QPR:$src)>;
7579 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
7580 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
7581 def : Pat<(v2f64 (bitconvert (v8f16 QPR:$src))), (v2f64 QPR:$src)>;
7582 def : Pat<(v2f64 (bitconvert (v8bf16 QPR:$src))), (v2f64 QPR:$src)>;
7583 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
7584 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
7586 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
7587 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
7588 def : Pat<(v2i64 (bitconvert (v8f16 QPR:$src))), (v2i64 QPR:$src)>;
7589 def : Pat<(v2i64 (bitconvert (v8bf16 QPR:$src))), (v2i64 QPR:$src)>;
7590 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
7591 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
7593 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
7594 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
7595 def : Pat<(v4f32 (bitconvert (v8f16 QPR:$src))), (v4f32 QPR:$src)>;
7596 def : Pat<(v4f32 (bitconvert (v8bf16 QPR:$src))), (v4f32 QPR:$src)>;
7597 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
7598 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
7600 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
7601 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
7602 def : Pat<(v4i32 (bitconvert (v8f16 QPR:$src))), (v4i32 QPR:$src)>;
7603 def : Pat<(v4i32 (bitconvert (v8bf16 QPR:$src))), (v4i32 QPR:$src)>;
7604 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
7605 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
7607 def : Pat<(v8f16 (bitconvert (v2f64 QPR:$src))), (v8f16 QPR:$src)>;
7608 def : Pat<(v8f16 (bitconvert (v2i64 QPR:$src))), (v8f16 QPR:$src)>;
7609 def : Pat<(v8f16 (bitconvert (v4f32 QPR:$src))), (v8f16 QPR:$src)>;
7610 def : Pat<(v8f16 (bitconvert (v4i32 QPR:$src))), (v8f16 QPR:$src)>;
7611 def : Pat<(v8f16 (bitconvert (v16i8 QPR:$src))), (v8f16 QPR:$src)>;
7613 def : Pat<(v8bf16 (bitconvert (v2f64 QPR:$src))), (v8bf16 QPR:$src)>;
7614 def : Pat<(v8bf16 (bitconvert (v2i64 QPR:$src))), (v8bf16 QPR:$src)>;
7615 def : Pat<(v8bf16 (bitconvert (v4f32 QPR:$src))), (v8bf16 QPR:$src)>;
7616 def : Pat<(v8bf16 (bitconvert (v4i32 QPR:$src))), (v8bf16 QPR:$src)>;
7617 def : Pat<(v8bf16 (bitconvert (v16i8 QPR:$src))), (v8bf16 QPR:$src)>;
7619 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
7620 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
7621 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
7622 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
7623 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
7625 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
7626 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
7627 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
7628 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
7629 def : Pat<(v16i8 (bitconvert (v8f16 QPR:$src))), (v16i8 QPR:$src)>;
7630 def : Pat<(v16i8 (bitconvert (v8bf16 QPR:$src))), (v16i8 QPR:$src)>;
7631 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
7691 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (VREV64q32 QPR:$src)>;
7692 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (VREV64q32 QPR:$src)>;
7693 def : Pat<(v2f64 (bitconvert (v8f16 QPR:$src))), (VREV64q16 QPR:$src)>;
7694 def : Pat<(v2f64 (bitconvert (v8bf16 QPR:$src))), (VREV64q16 QPR:$src)>;
7695 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (VREV64q16 QPR:$src)>;
7696 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (VREV64q8 QPR:$src)>;
7698 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (VREV64q32 QPR:$src)>;
7699 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (VREV64q32 QPR:$src)>;
7700 def : Pat<(v2i64 (bitconvert (v8f16 QPR:$src))), (VREV64q16 QPR:$src)>;
7701 def : Pat<(v2i64 (bitconvert (v8bf16 QPR:$src))), (VREV64q16 QPR:$src)>;
7702 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (VREV64q16 QPR:$src)>;
7703 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (VREV64q8 QPR:$src)>;
7705 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (VREV64q32 QPR:$src)>;
7706 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (VREV64q32 QPR:$src)>;
7707 def : Pat<(v4f32 (bitconvert (v8f16 QPR:$src))), (VREV32q16 QPR:$src)>;
7708 def : Pat<(v4f32 (bitconvert (v8bf16 QPR:$src))), (VREV32q16 QPR:$src)>;
7709 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (VREV32q16 QPR:$src)>;
7710 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (VREV32q8 QPR:$src)>;
7712 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (VREV64q32 QPR:$src)>;
7713 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (VREV64q32 QPR:$src)>;
7714 def : Pat<(v4i32 (bitconvert (v8f16 QPR:$src))), (VREV32q16 QPR:$src)>;
7715 def : Pat<(v4i32 (bitconvert (v8bf16 QPR:$src))), (VREV32q16 QPR:$src)>;
7716 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (VREV32q16 QPR:$src)>;
7717 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (VREV32q8 QPR:$src)>;
7719 def : Pat<(v8f16 (bitconvert (v2f64 QPR:$src))), (VREV64q16 QPR:$src)>;
7720 def : Pat<(v8f16 (bitconvert (v2i64 QPR:$src))), (VREV64q16 QPR:$src)>;
7721 def : Pat<(v8f16 (bitconvert (v4f32 QPR:$src))), (VREV32q16 QPR:$src)>;
7722 def : Pat<(v8f16 (bitconvert (v4i32 QPR:$src))), (VREV32q16 QPR:$src)>;
7723 def : Pat<(v8f16 (bitconvert (v16i8 QPR:$src))), (VREV16q8 QPR:$src)>;
7725 def : Pat<(v8bf16 (bitconvert (v2f64 QPR:$src))), (VREV64q16 QPR:$src)>;
7726 def : Pat<(v8bf16 (bitconvert (v2i64 QPR:$src))), (VREV64q16 QPR:$src)>;
7727 def : Pat<(v8bf16 (bitconvert (v4f32 QPR:$src))), (VREV32q16 QPR:$src)>;
7728 def : Pat<(v8bf16 (bitconvert (v4i32 QPR:$src))), (VREV32q16 QPR:$src)>;
7729 def : Pat<(v8bf16 (bitconvert (v16i8 QPR:$src))), (VREV16q8 QPR:$src)>;
7731 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (VREV64q16 QPR:$src)>;
7732 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (VREV64q16 QPR:$src)>;
7733 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (VREV32q16 QPR:$src)>;
7734 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (VREV32q16 QPR:$src)>;
7735 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (VREV16q8 QPR:$src)>;
7737 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (VREV64q8 QPR:$src)>;
7738 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (VREV64q8 QPR:$src)>;
7739 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (VREV32q8 QPR:$src)>;
7740 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (VREV32q8 QPR:$src)>;
7741 def : Pat<(v16i8 (bitconvert (v8f16 QPR:$src))), (VREV16q8 QPR:$src)>;
7742 def : Pat<(v16i8 (bitconvert (v8bf16 QPR:$src))), (VREV16q8 QPR:$src)>;
7743 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (VREV16q8 QPR:$src)>;
7755 def : Pat<(VT (ARMVectorRegCastImpl (VT2 QPR:$src))), (VT QPR:$src)>;
7766 def : Pat<(byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
7767 (VST1q8 addrmode6:$addr, (VREV64q8 QPR:$value))>;
7770 def : Pat<(hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
7771 (VST1q16 addrmode6:$addr, (VREV64q16 QPR:$value))>;
8078 (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
8080 (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
8082 (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
8084 (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
8086 (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
8088 (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
8090 (REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
8106 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8110 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8114 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8118 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8123 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
8127 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
8131 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
8138 (VBICiv8i16 QPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
8140 (VBICiv4i32 QPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
8982 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
8987 (VMVNq QPR:$Vd, QPR:$Vm, pred:$p)>;
9010 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9012 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9014 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9016 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9018 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9020 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9022 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9025 (VCGEhq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9048 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9050 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9052 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9054 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9056 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9058 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9060 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9063 (VCGThq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
9069 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
9079 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
9081 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
9083 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
9089 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
9093 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
9140 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
9189 def BF16VDOTS_VDOTQ : BF16VDOTS<1, QPR, "vdot", v4f32, v8bf16>;
9192 defm BF16VDOTI_VDOTQ : BF16VDOTI<1, QPR, "vdot", v4f32, v8bf16, (EXTRACT_SUBREG QPR:$Vm, dsub_0)>;
9199 [(set (v4f32 QPR:$dst), (int_arm_neon_bfmmla (v4f32 QPR:$Vd),
9200 (v8bf16 QPR:$Vn),
9201 (v8bf16 QPR:$Vm)))]> {
9207 def VMMLA : BF16MM<1, QPR, "vmmla">;
9211 (outs QPR:$dst), (ins QPR:$Vd, QPR:$Vn, QPR:$Vm),
9213 [(set (v4f32 QPR:$dst),
9214 (OpNode (v4f32 QPR:$Vd),
9215 (v8bf16 QPR:$Vn),
9216 (v8bf16 QPR:$Vm)))]> {
9225 def "" : N3VLaneCP8<0, 0b11, T, 1, (outs QPR:$dst),
9226 (ins QPR:$Vd, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$idx),
9236 (v4f32 (OpNode (v4f32 QPR:$Vd),
9237 (v8bf16 QPR:$Vn),
9238 (v8bf16 (ARMvduplane (v8bf16 QPR:$Vm),
9240 (!cast<Instruction>(NAME) QPR:$Vd,
9241 QPR:$Vn,
9242 (EXTRACT_SUBREG QPR:$Vm,
9251 (outs DPR:$Vd), (ins QPR:$Vm),