Lines Matching refs:RdLo

4275   bits<4> RdLo;
4280   let Inst{15-12} = RdLo;
4287   bits<4> RdLo;
4292   let Inst{15-12} = RdLo;
4358 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
4360                     "smull", "\t$RdLo, $RdHi, $Rn, $Rm",
4361                     [(set GPR:$RdLo, GPR:$RdHi,
4366 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
4368                     "umull", "\t$RdLo, $RdHi, $Rn, $Rm",
4369                     [(set GPR:$RdLo, GPR:$RdHi,
4374 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
4375 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4378                             [(set GPR:$RdLo, GPR:$RdHi,
4380           (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4384 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4387                             [(set GPR:$RdLo, GPR:$RdHi,
4389           (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4396 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
4398                     "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4399          RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4401 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
4403                     "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4404          RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4407 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
4410                     "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4411          RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4413   bits<4> RdLo;
4418   let Inst{15-12} = RdLo;
4424     "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
4425 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4428              (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4432 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4435              (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4584         (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4586         IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4587         RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
4640   bits<4> RdLo;
4643   let Inst{15-12} = RdLo;
4658   def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4661                   !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">,
4662                   RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
4665   def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4668                   !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">,
4669                   RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
6404 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6405             (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6407 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6408             (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6410 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6411             (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6413 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6414             (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,